//----- Testbench -----

// Timescale: one time unit = 1ns (e.g., delay specification of #42 means 42ns of time), and
// simulator resolution is 0.1 ns
`timescale 1ns / 100ps

module DigitDisplay_TESTBENCH;

// Input stimulus:
reg	i$Clock50MHz;
reg	i$MasterReset;
reg	[7:0]	i$RightByte;
reg	[7:0]	i$LeftByte;

// Output connections:
wire	o$Segment_a;
wire	o$Segment_b;
wire	o$Segment_c;
wire	o$Segment_d;
wire	o$Segment_e;
wire	o$Segment_f;
wire	o$Segment_g;
wire	o$Segment_dp;
wire	o$Digit_Right;
wire	o$Digit_MiddleRight;
wire	o$Digit_MiddleLeft;
wire	o$Digit_Left;


//Instantiate the DUT (device under test):
DigitDisplay DUT (
	// Inputs:
	.i$Clock50MHz ( i$Clock50MHz ),	// System
	.i$MasterReset ( i$MasterReset ),	// Master
	.i$RightByte ( i$RightByte ),	// Value
	.i$LeftByte ( i$LeftByte ),	// Value

	// Outputs:
	.o$Segment_a ( o$Segment_a ),	// LED
	.o$Segment_b ( o$Segment_b ),	// etc.
	.o$Segment_c ( o$Segment_c ),
	.o$Segment_d ( o$Segment_d ),
	.o$Segment_e ( o$Segment_e ),
	.o$Segment_f ( o$Segment_f ),
	.o$Segment_g ( o$Segment_g ),
	.o$Segment_dp ( o$Segment_dp ),	// LED
	.o$Digit_Right ( o$Digit_Right ),	// Rightmost
	.o$Digit_MiddleRight ( o$Digit_MiddleRight ),	// etc.
	.o$Digit_MiddleLeft ( o$Digit_MiddleLeft ),
	.o$Digit_Left ( o$Digit_Left )
);

	// Specify input stimulus:

initial begin
	// Notify user about the specific value of the frequency divider counter
	$display("NOTE: Using %d as the frequency divider counter upper limit\n",DUT.p$UpperLimit);

	// Initial values for input stimulus:
	i$Clock50MHz = 1'b0;
	i$MasterReset = 1'b1;
	i$RightByte = 8'h42;
	i$LeftByte = 8'h5E;

	// Take out of reset
	#10 i$MasterReset = 1'b0;

	// Run for awhile
	#200 $finish;
end

	// Template for master clock. Uncomment and modify signal name as needed.
	// Remember to set the initial value of 'Clock' in the 'initial' block above.
always #5 i$Clock50MHz = ~i$Clock50MHz;


endmodule