module Pattern_Generator (

// This module will accept a clock
// signal as input and produce an
// interesting pattern on a seven-segment
// LED display digit.

   // Inputs
   I$Clock,  // Master clock, rising edge
   I$Reset_,  // Master reset, asynchronous, active high

   // Outputs
   O$LEDa_,   // LED digit segments
   O$LEDb_,
   O$LEDc_,
   O$LEDd_,
   O$LEDe_,
   O$LEDf_,
   O$LEDg_
);

// Declare port modes
input I$Clock, I$Reset_;
output O$LEDa_;
output O$LEDb_;
output O$LEDc_;
output O$LEDd_;
output O$LEDe_;
output O$LEDf_;
output O$LEDg_;

// Declare registered variables
reg [2:0] Count;
reg [7:0] Decoder;
reg O$LEDa_;
reg O$LEDb_;
reg O$LEDc_;
reg O$LEDd_;
reg O$LEDe_;
reg O$LEDf_;
reg O$LEDg_;


// Declare wire variables

// Three-bit UP counter
always @ (posedge I$Clock or negedge I$Reset_)
   if (I$Reset_==0)
      Count <= 0;
   else
      Count <= Count + 1;

// Three-to-eight decoder
always @ (Count)
   case (Count)
      0 : Decoder <= 8'b0000_0001;
      1 : Decoder <= 8'b0000_0010;
      2 : Decoder <= 8'b0000_0100;
      3 : Decoder <= 8'b0000_1000;
      4 : Decoder <= 8'b0001_0000;
      5 : Decoder <= 8'b0010_0000;
      6 : Decoder <= 8'b0100_0000;
      7 : Decoder <= 8'b1000_0000;
      default: Decoder <= 8'b0000_0000;
   endcase

// LED driver
always @ (Decoder) begin
   O$LEDa_ <= ~(Decoder[0] | Decoder[1]);
   O$LEDb_ <= ~(Decoder[1] | Decoder[2]);
   O$LEDc_ <= ~(Decoder[2] | Decoder[3]);
   O$LEDd_ <= ~(Decoder[3] | Decoder[4]);
   O$LEDe_ <= ~(Decoder[4] | Decoder[5]);
   O$LEDf_ <= ~(Decoder[5] | Decoder[6]);
   O$LEDg_ <= ~(Decoder[6] | Decoder[7]);
end

endmodule