Index to CUPL Help

Overview

Getting Started

Menu Command

Language Syntax

Compile Option

Simulate Option

Device Utility

NetList Translator Utility

Error Message

Message Window

Device Node Numbering

Working Enviroment

Key Word


Overview

The key features of the CUPL package include:

Universal applicability. CUPL supports products from all manufacturers of PLDs, enabling a user to put the same functional logic into physically different parts, to create a second source at the socket. CUPL produces a standard type of file called JEDEC. This is a download file that is compatible with any logic programmer that uses JEDEC files. The CUPL language translator (PTOC) converts PALASM designs to CUPL, enabling the use of any PALASM designs.

A high-level language. Expression substitution for equations, shorthand notation for lists, address ranges, and bit fields are available to save design time.

CUPL simplifies Boolean expressions by the distributive property and DeMorgans Theorem.

State machine syntax provides a powerful means of implementing any synchronous application using either Mealy or Moore state machine models.

Truth table syntax provides a way to clearly express certain logic descriptions.

User-defined functions allow the creation of  keywords for use by CUPL.

Flexible documentation. CUPL provides a template file for standard fill in the blanks documentation and allows the placement of free-form comments throughout a design.

CUPLs comprehensive error-checking capability generates detailed error messages designed to lead to the source of any problems.

Powerful minimizer and simulation programs. CUPL contains the fastest and most powerful minimizer offered for programmable logic equation reduction, featuring four levels of minimization.

The CUPL simulation program enables logic to be simulated prior to using a PLD. This feature prevents blown devices and helps debug system-level problems. Test vectors verified by CSIM can be downloaded to a logic programmer.


Getting Started

This section assumes that the user has had some experience with programmable devices. A basic understanding of logic and logic gates, and how they relate to the design of programmed devices, is required.

Examine the Design Task

Take a close look at the design that is needed. Remember that state-machine, Boolean equations, or truth tables are available for the design. Try to determine which type of syntax best suits the design task that is being worked on.

Create the CUPL Source File

Use the template file provided and remove the sections that do not apply. Remember to edit the header to reflect the new file that is being created.

Formulate the Equations

Equations must be written in CUPL syntax to specify the logic desired. This can be in Boolean, state-machine, or truth table format.

Choosing a Target Device

o	Make sure that there is a sufficient number of input pins.

o	Check that the number of registered and non-registered output pins is sufficient for the design.

o	Ensure that the device has three-state output control, if you need it.

o	Check that the device can adequately handle the number of product terms required.

Making Pin Assignments

Assign the inputs and outputs of the design to the pins of the device. Make sure that the device is being used properly by consulting the reference material available from the manufacturer.

Running CUPL

Decide which file formats will be needed for downloading and simulation. A choice of four minimizers is available (M1M4). CUPL will use M1 minimization if none is specified.

SIMPLE GATES EXAMPLE

This section will explain in detail the creation of a simple gates program for a PLD. This design is supplied as one of the example files. It is appropriately called GATES.PLD. This design gives a simple set of inputs and generates output simulating some simple gates. The outputs are labeled to reflect the function of their gate; for example, the AND gate has an output labeled AND.

Name             Gates;
Partno           CA0001;
Date             07/16/87;
Designer         G Woolheiser;
Company          ATI;
Location         San Jose, CA.;
Assembly         Example

/******************************************************/
/*                                                    */
/* This is an example to demonstrate how CUPL         */
/* compiles simple gates       .                      */
/*                                                    */
/******************************************************/
/*   Target Devices: P16L8, P16P8, EP300, and 82S153  */
/******************************************************/

Figure 1.  GATES.PLD header section

The first part of the file provides archival information and a description of the intended function of the design, including compatible PLDs.

First, there is the Name line, which CUPL uses to name the output files by adding extensions. Partno specifies the Companys proprietary part number, issued by manufacturing, for a particular PLD design. The part number is not the type of the target PLD. Date is used to specify the date of compilation. The date should be changed to the current date as a good documentation practice. Designer should be the designers name or the name of the design team. Assembly is used to specify  the assembly name or number of the PC board on which the PLD will be used. Use the abbreviation ASSY if desired.

/* Inputs:   define inputs to build simple gates      */
Pin 1 = a;
Pin 2 = b;

/* Outputs:   define outputs as active HI levels

   For PAL16L8 and PAL16LD8, De Morgan's Theorem is
   applied to invert all outputs due to fixed
   inverting buffer in the device.                    */

Pin 12 = inva;
Pin 13 = invb;
Pin 14 = and;
Pin 15 = nand;
Pin 16 = or;
Pin 17 = nor;
Pin 18 = xor;
Pin 19 = xnor;

Figure 2.  GATES.PLD pin declaration section

Pin declarations are made corresponding to the inputs and outputs in the design diagram. The gates in this example require two inputs, which are passed through the gates as necessary. a and b are names for the input pins. Next, names are assigned to the output pins. The names chosen are descriptive of the function being performed. The use of descriptive names is encouraged, as it makes files easier to debug and update at a later time.

/* Logic:   examples of simple gates expressed in CUPL */

inva = !a;	/* inverters	*/
invb = !b;
and  = a & b;	/* and gate	*/
nand = !(a & b);	/* nand gate	*/
or   = a # b;	/* or gate	*/
nor = !(a # b);	/*nor gate	*/
xor = a $ b;	/*exclusive or gate	*/
xnor  = !(a $ b);	/*exclusive nor gate	*/

Figure 3.  GATES.PLD logic equation section

In the Logic section of the file, equations describe each of the gates in the design. Boolean syntax is used to specify each output pin as a function of the input pins a and b.

For the PAL16L8 and PAL16LD8 devices, which contain fixed inverting buffers, CUPL applies DeMorgans Theorem to invert all outputs because they were all declared active-HI in the pin list. For example, during compilation, CUPL converts the following equation for an OR gate, on an output pin that has been declared as active-HI:

or = a # b ;

to the following single expanded product term (as shown in the documentation file):

or => !a & !b

The devices chosen for this design were selected because they fit the criteria, as specified earlier, for choosing a device. They have an adequate number of pins, both input and output. They have tri-state control. The number of registered and non-registered pins fits our design, and the device can handle the number of product terms.

COMPILING THE SOURCE FILE

This section will show you how to compile and simulate a source file.

1) From the Options menu in WINCUPL, Choose Compiler Options... This will bring up the Compiler options dialog.box.

2a) Click on the Select Files. This will bring up the Select PLD File dialog box.

Specify the path to your source file.  If you want WINCUPL to simulate after compile select the Simulate button from the Miscellaneous options menu. When you are done click OK.

3) Click the Output file button . This will bring up the Output Format dialog box. Click the equations check box. If you want WINCUPL to generate a JEDEC file you must select the JEDEC/POF/PRG check box. If

Notes:

1) If you want WINCUPL to generate a JEDEC file you must select the JEDEC check box

Go to the Run menu and choose Device specific compile..  This will execute CUPL. A documentation file (GATES.DOC) willbe produced so that the expanded equations generated by CUPL may be viewed. The target device is a ATF16V8B and the source file is GATES.PLD.

After running CUPL, open the file GATES.DOC, which has the expanded listing generated by CUPL. This shows how CUPL expands the logic equations when it compiles the design for the device chosen.

In order to see how CUPL reports errors, edit the source file GATES.PLD and remove the semicolon at the end of one of the assignment statements. Now run CUPL as follows:

From the compiler options dialog, click the output button and turn on the "Listing file" option.  Go to the Run menu and choose "Device specific compile".

After it has finished, take a look at the file GATES.LST to see how CUPL reports errors. Notice that an error line appears next to the error, and there are line numbers at the beginning of each line.

SIMULATING A DESIGN

Now the design will be simulated using CSIM. Test vectors must be created for the simulator to function. Test vectors specify the expected functional operation of a PLD by defining the outputs as a function of the inputs. Test vectors are also used to do functional testing of a device once it has been programmed, to see if the device functions as expected.

CSIM needs a test specification source file. For this example, it will be called GATES.SI. This file has a description of the function of the device in the circuit.

CSIM compares the input pin and output pin test values in the GATES.SI file with the actual values that are calculated from the logic equations in the absolute file GATES.ABS created by CUPL.

To simulate the design: .

1) Select the Absolute file option under Output  in the Compiler Options.. dialog.

Go to the Run menu and choose Device Specific Compile.. When this is complete, the absolute file will be generated and the design can now be simulated.

2) From the Options menu in WINCUPL choose Simulate Options..

3) Click on the Select Files button to select the file you want to simulate. Specify the path to the Simulation Input File (*.si file) for your design and Click OK.

If you have not specified a device type in your simulation input file, select the Device button. A list of target devices will be displayed. Select one and click OK.

4) From the Run menu choose Device Specific Simulate. This will run the simulator.

NOTES:

1) CSIM will not run unless the Absolute file is created.

2) It is also possible to generate the absolute file and simulate the design in a single step.
 From the Compiler Options.. menu, select the Simulate and Absolute File options. WINCUPL will produce the absolute file and run the simulator. You do not have to run the simulator as a separate step.

/* Order:  define order, polarity, and output	*/
/* spacing of stimulus and response values 	*/

Order:  a, %2, b, %4, inva, %3, invb, %5, and, %8,
        nand, %7, or, %8, nor, %7, xor, %8, xnor;

/* Vectors:  define stimulus and response values, with header    */
/*           and intermediate messages for the simulator listing */
/* Note:     Don't Care state (X) on inputs is reflected in      */
/*           outputs where appropriate.                          */
Vectors:
00 HHLHLHLH
01 HLLHHLHL
10 LHLHHLHL
11 LLHLHLLH
1X LXXXHLXX
X1 XLXXHLXX
0X HXLHXXXX
X0 XHLHXXXX
XX XXXXXXXX

GATES.SI simulation section

Figure 5 shows the simulator output file. The inputs are listed with the corresponding outputs.

===================================================================
              i   i             n                          x
              n   n     a       a              n     x     n
              v   v     n       n       o      o     o     o
      a  b    a   b     d       d       r      r     r     r
===================================================================

0001: 0  0    H   H     L       H       L      H     L     H
0002: 0  1    H   L     L       H       H      L     H     L
0003: 1  0    L   H     L       H       H      L     H     L
0004: 1  1    L   L     H       L       H      L     L     H
0005: 1  X    L   X     X       X       H      L     X     X
0006: X  1    X   L     X       X       H      L     X     X
0007: 0  X    H   X     L       H       X      X     X     X
0008: X  0    X   H     L       H       X      X     X     X
0009: X  X    X   X     X       X       X      X     X     X

GATES.SO simulation results


Data Flow


command
Menu Command

File Menu

New

Open

Save

Save As

Print

Exit

Edit Menu

Cut

Paste

Copy

Delete

Search

Line To

Option Menu

Compile

Simulate

Preference

Run Menu

Device Dependent Compile

Device Dependent Simulate

Device Independent Compile

Device Independent Simulate

Utility Menu

Device Library

Project

Load

Save

Window Menu

Cascade

Tile

Arrange Icon

Close All


enviroment
Working Enviroment

CUPL  for Windows provides a configuration file CUPL.CFG which contains the default device library, working directory, and user specified device library path. This provides great convenience for the users. You can store a design file in one directory, and an updated device library in another directory, Every time CUPL is invoked, it remenber the working directory and library path. The content of CUPL.CFG can be modified by activating preference command of the option menu.

Another useful feature of CUPL for Windows is the project file. Each design can keep its own project file which contains the compiler and simulator options, the selected device and the selected device library. The project file must be the same file name as the design file and with the PRJ file extension. The project file must stay in the same directory as the design file, When you open or select a design file, CUPL automatically loads the project file (if it exists). The project file can be saved either by choosing Save Project of Project menu or by default when you quit CUPL.  The project file does not save the currently selected device.  If you want to choose a device automatically when you open a file, put the desired device mnemonic in the "Device" field in the header section of the source file.


File - New

Open a template file. The template file can be specified in Option-Preference dialog box.


File - Open

Open any text file, load it into an editor window. If a project file exists, CUPL will automatically load this project file.


File - Save

Save the contens of the curret active editor window. If the contents is not modified, this operation does nothing.


File - Save As

Popup a dialog box to ask the file name and save the contents of the current active editor window. If the file already exists, another dialog box will ask you to confirm this operation.


File - Print

Send  the contents of the curret active editor window to Windows default printer using the default font.


File - Exit

Quit CUPL and save curent setting into CUPL.CFG if check box of "save config when exit" is ON, save current setting into project file if check box of "save project when exit" is ON.


Edit - Cut

Removes the selected text from the document and puts it on the Clipboard. This command is unavailable if nothing is selected.


Edit - Paste

Insert a copy of the Clipboard contents at the insertion point. This command is unavailable if the Clipboard is empty.


Edit - Copy

Copies the selected text onto the Clipboard. This command is unavailable if nothing is selected.


Edit - Delete

Deletes the selected text from the document. This command is unavailable if nothing is selected.


Edit - Search

Searches for specified text pattern in the active windows. A dialog box lets you enter the search pattern.


Edit - Line To

Move cursor to the specified line. A dialog box lets you to enter the line number.


Option - Compile

The Option menu lets you set compiler options. The options are selectable in the dialog boxes. More details on these options are explained in the CUPL PLD/FPGA Language Compiler Manual. The Output file button in the compiler option dialog box lets you select various output files from CUPL. When this button is selected, another dialog box called Output Format is popped up.

Use the Select Library button to select a different library file. When this button is clicked, a dialog box  will appear to let you to select a device file. The default library is the device library file you specified in the Preference command. Initially, the default library is set to CUPL.DL  with the path  where CUPL for Windows was originally installed. When the Select Device button is pressed, a device selection dialog box will appear. The devices are listed by their category and package type. For example, if you want to use the ATV750B in a PLCC package, you need to select device type EPLD and choose the LCC package. Now you can select ATV750BLCC by double-clicking on it.

The Select File button allows you to choose a PLD or SI file. The difference between selecting a file here and selecting a file in FILE OPEN command is that a file selected in FILE OPEN command will automatically create an EDIT window  and load the selected file into that EDIT Window. When you select a file from this dialog, no EDIT Window is created. The editor in CUPL can only edit files smaller than 32k. Larger files can still be compiled by using the Select File button in these dialogs. This feature also allows you to use you own choice of text editor.


Option - Simulate

The Option menu lets you set simulator options. The options are selectable in the dialog boxes. More details on these options are explained in the CUPL PLD/FPGA Language Compiler Manual. The Output file button in the compiler option dialog box lets you select various output files from CUPL. When this button is selected, another dialog box called Output Format is popped up.

Use the Select Library button to select a different library file. When this button is clicked, a dialog box  will appear to let you to select a device file. The default library is the device library file you specified in the Preference command. Initially, the default library is set to CUPL.DL  with the path  where CUPL for Windows was originally installed. When the Select Device button is pressed, a device selection dialog box will appear. The devices are listed by their category and package type. For example, if you want to use the ATV750B in an PLCC package, you need to select device type EPLD and choose the LCC package. Now you can select ATV750BLCC by double-clicking on it.

The Select File button allows you to choose a PLD or SI file. The difference between selecting a file here and selecting a file in FILE OPEN command is that a file selected in FILE OPEN command will automatically create an EDIT window  and load the selected file into that EDIT Window. When you select a file from this dialog, no EDIT Window is created. The editor in CUPL can only edit files smaller than 32k. Larger files can still be compiled by using the Select File button in these dialogs. This feature also allows you to use you own choice of text editor.


Select File

Select File button allowas user to choose a PLD or SI file. The difference between selecting a file using select file button and select a file in FILE OPEN command is that a file selected in FILE OPEN command will automatically create an EDIT window and load the selected file into that EDIT window. When you select a file from select file button, no EDIT Windows is created. The editor in CUPL can only load a file which is smaller than 64k. This select file buffon allows user to select a large file (> 64k) to compile.


Select Device

Select Device button allows user to select a device for his design. The devices are listed by their category and package type. You need to select the type and package, then select device name. For example, choosing ATV750B in a PLCC package, select type as EPLD and package type as LCC.


Select Library

You can select a library instead using default library. When this button is pressed, a file select dialog box will appears. The directory path of this library select box can be set by option preference.


Output File

Output file selection dialog lets user to select various output file options. The output file selections are grouped into three groups.


Option - Preference

The Preference command lets you set the following options:

Default Library -- This library is used when you do not specify a device library. The default library name must include the whole path and drive.

Library Path -- This is the path to the directory where libraries are stored.  When using the -u flag, CUPL searches this directory for all available library updates (*.DL).

Working Dir. -- This is the directory that contains your design files.

Save config when exit -- If this check box is checked, CUPL.CFG will automatically  be updated when you exit from CUPL.

Save project when exit -- If this check box is checked, the currently selected design's project will be automatically updated when you exit from CUPL.


Run - Device Specific compile

Compile a specified design(PLD file) using specified device. If a specified device is virtual, the function of this command is same as Run-Device Independent compile.


Run - Device dependent simulate

Simulate a specified design using specified device. If a specified device is virtual the function of this command is same as Run-Device independent simulate.


Run - Device independent compile

Compile a specified design using virtual device. If a device is specified in PLD file or a device selected in device selection dialog box, this device will be ignored.


Run - Device independent simulate

Simulate a specified design using virtual device. If a device is specified in PLD file or a device selected in device selection dialog box, this device will be ignored.


Utility - Device library

The DEVICE LIBRARY Utility  performs the following functions:

1. Builds libraries.

2. List device information in short form.

3. List device information in long form.

4. List valid extensions for a device.

The details of these functions are described in CUPL PLD/FPGA Language Compiler Manual.


Project - Save

A project file contains design settings for a particular design. It contains all CUPL compile or simulation options and the selected library if any. The save command lets you explicitly save these design settings. (Implicit saving is automatically done when exiting CUPL).


Project - Load

A project file contains design setting for a particular design. It contains all CUPL compile or simulation options and selected library if any. The load command allows you to explicitly load these design setting. (Implicit loading will be done when a PLD file is loaded).


Window - Cascade

Cascade all opened documents


Window - Tile

Tile all opened documents


Window - Arrange icon

Arrange all documents in icon.


Window - Close all

Close all opened documents


Language Syntax

Preprocessor Command

Logical Operator

Index Variable

Extension

Truth Table

State Machine


LIAISON

LIAISON is a netlist translator that allows you to use a schematic editor to do logic design.  LIAISON reads the netlist and writes a PLD file for the compiler.  At the time of this release LIAISON is not available for Windows.  Please contact LOGICAL DEVICES or your local representative for more information if you want to do schematic design with CUPL.


Message Window

Message window is used to display CUPL waring and error messages. Any line of the text in the message window can be selected and unselected by cliking left button of the mouse. If an error message is selected and a F1 key is pressed, CUPL will automatically display HELP window and locate to that error message. If the line selected is not an error message, CUPL will diaplay HELP window and locate the Error Message topic.


Error Message

CUPL error messages are intended to be self-explanatory. This appendix provides additional information describing them.

Some of the CUPL programs, such as CUPL and CSIM, are composed of individual modules. Error messages are numbered and listed according to the program and module in which they occur. The suffix to the error message number identifies the program and module.

Error Message Module Prefixes

Module	Prefix

CUPL processor	ck

CUPLX preprocessor	cx

CUPLA source file parser	ca

CUPLB equation fitter	cb

CUPLM minimizer	cm

CUPLC fusemap generator	cc

CSIM processor	sk

CSIMA logic simulator	sa

CBLD device library manager	ba

This appendix lists the error messages by modules in the same order as they appear in the above table. The error messages within each module are listed in numerical order.

CUPL provides three levels of error messages: warnings, errors, and fatals.

warnings  do not prevent CUPL from continuing, but indicate a problem that should be corrected.

errors  allow CUPL to continue but must be corrected before future compiles.

fatals  prevent CUPL from continuing and must be corrected.

Note

Error messages with indexes greater than 1000 are program errors.  This section does not individually list program errors. Possible causes for program errors are bad data in a source file caused by disk errors or word processors in document mode; or previous errors continuing to propagate unexpected circumstances. If the cause of a program error cannot be determined, gather as much information as possible on the conditions in effect when the error occurred, then call CUPL support.


preprocessor
Preprocessor Commands

The preprocessor portion of CUPL operates on the source file before it is passed to the parser and other sections of the compiler. The preprocessor commands add file inclusion, conditional compilation, and string substitution capabilities to the source processing features of CUPL. Following table lists the available preprocessor commands. Each command is described in detail in this section.

$DEFINE	$IFDEF	$UNDEF
$ELSE	$IFNDEF	$REPEAT
$ENDIF	$INCLUDE	$REPEND
$MACRO	$MEND

The dollar sign ($) is the first character in all preprocessor commands and must be used in column one of the line. Any combination of uppercase or lowercase letters may be used to type these commands.


$DEFINE

This command replaces a character string by another specified operator, number, or symbol. The format is as follows:

$DEFINE argument1 argument2

where

argument1 is a variable name or special ASCII character.

argument2 is a valid operator, a number, or a variable name.

Argument1 is replaced by argument2 at all locations in the source specification after the $DEFINE command is given (or until the preprocessor encounters an $UNDEF command). The replacement is a literal string substitution made on the input file before being processed by the CUPL compiler. Note that no semicolon or equal sign is used for this command.

The $DEFINE command allows numbers or constants to be replaced with symbolic names, for example:

$DEFINE	ON	'b'1

$DEFINE	OFF	b'0

$DEFINE	PORTC	'h'3F0

The $DEFINE command also allows creation of a personal set of logical operators. For example, the following define an alternate set of operators for logic specification:

$DEFINE	{	/*	Alternate Start Comment

$DEFINE	}	*/	Alternate End Comment

$DEFINE	/	!	Alternate Negation

$DEFINE	*	&	Alternate AND

$DEFINE	+	#	Alternate OR

$DEFINE	:+:	$	Alternate XOR


$UNDEF

This command reverses a $DEFINE command. The format is as follows:

$UNDEF argument

where

argument is an argument previously used in a $DEFINE command.

Before redefining a character string or symbol defined with the $DEFINE command, use the $UNDEF command to undo the previous definition.


$INCLUDE

This command includes a specified file in the source to be processed by CUPL. The format is as follows:

$INCLUDE filename

where

filename is the name of a file in the current directory.

File inclusion allows standardizing a portion of a commonly used specification. It is also useful for keeping a separate parameter file that defines constants that are commonly used in many source specifications. The files that are included may also contain $INCLUDE commands, allowing for nested include files. The named file is included at the location of the $INCLUDE command.

For example, the following command includes the FIT1500.M (Atmel ATF1500 fitter macro Macro listing file) in a source file.

$INCLUDE FIT1500.M

$DEFINE commands can also specify the following alternate set of logical operators.

$DEFINE 	/	!	Alternate Negation

$DEFINE	*	&	Alternate AND

$DEFINE	+	#	Alternate OR

$DEFINE	:+:	$	Alternate XOR

$DEFINE	{	/*	Alternate Start Comment

$DEFINE	}	*/	Alternate End Comment


$IFDEF

This command conditionally compiles sections of a source file. The format is as follows:

$IFDEF argument

where

argument may or may not have previously been defined with a $DEFINE command.

When the argument has previously been defined, the source statements following the $IFDEF command are compiled until the occurrence of an $ELSE or $ENDIF command.

When the argument has not previously been defined, the source statements following the $IFDEF command are ignored. No additional source statements are compiled until the occurrence of an $ELSE or $ENDIF command.

One use of $IFDEF is to temporarily remove source equations containing comments from the file. It is not possible to comment out the equations because comments do not nest. The following example illustrates this technique. NEVER is an undefined argument.

$IFDEF NEVER

out1=in1 & in2;	/* A Simple AND Function */

out2=in3 # in4;	/* A Simple OR Function */

$ENDIF

Because NEVER is undefined, the equations are ignored during compilation; that is, they function as comments.


$IFNDEF

This command sets conditions for compiling sections of the source file.

$IFNDEF argument

where

argument may or may not have previously been defined with a $DEFINE command.

The $IFNDEF command works in the opposite manner of the $IFDEF command. When the argument has not previously been defined, the source statements following the $IFNDEF command are compiled until the occurrence of an $ELSE or $ENDIF command.

If the argument has previously been defined, the source statements following the $IFNDEF command are ignored. No additional source statements are compiled until the occurrence of an $ELSE or $ENDIF command.

One use of $IFNDEF is to create a single source file containing two mutually exclusive sets of equations. Using an $IFNDEF and $ENDIF command to set off one of the sets of equations, quick toggling is possible between the two sets of equations by defining or not defining the argument specified in the $IFNDEF command.

For example, some devices contain common output enable pins that directly control all the tri-state buffers, whereas other devices contain single product terms to enable each tri-state buffer individually. In the following example, the argument, COMMON_OE has not been defined, so the equations that follow are compiled. Any equations following $ENDIF are not compiled.

$IFNDEF	COMMON_OE

pin 11	= !enable;	/* input pin for OE*/

[q3,q2,q1,q0].oe	= enable;	/* assign tri-state*/

/* equation for 4*/

/* outputs	*/

$ENDIF

If the device has common output enables, no equations are required to describe it. Therefore, in the above example, for a device with common output enables, define COMMON_OE so the compiler skips the equations between $IFNDEF and $ENDIF.


$ENDIF

This command ends a conditional compilation started with the $IFDEF or $IFNDEF commands. The format is as follows:

$ENDIF

The statements following the $ENDIF command are compiled in the same way as the statements preceding the $IFDEF or $IFNDEF commands. Conditional compilation may be nested, and for each level of nesting of the $IFDEF or $IFNDEF command, an associated $ENDIF must be used.

The following example illustrates the use of $ENDIF with multiple levels of nesting.

$IFDEF	prototype_1

pin 1	= set;	/* Set on pin 1*/

pin 2	= reset;	/* Reset on pin 2*/

$IFDEF	prototype_2

pin 3	= enable;	/* Enable on pin 3*/

pin 4	= disable;	/* Disable on pin 4*/

$ENDIF

pin 5	= run;	/* Run on pin 5*/

pin 6	= halt;	/* Halt on pin 6*/

$ENDIF


$endif
$ELSE

This command reverses the state of conditional compilation as defined with $IFDEF or $IFNDEF. The format is as follows:

$ELSE

If the tested condition of the $IFDEF or $IFNDEF commands is true (that is, the statements following the command are compiled), then any source statements between an $ELSE and $ENDIF command are ignored.

If the tested condition is false, then any source statements between the $IFDEF or $IFNDEF and $ELSE command are ignored, and statements following $ELSE are compiled.

For example, many times the production printed circuit board uses a different pinout than does the wire-wrap prototype. In the following example, since Prototype has been defined, the source statements following $IFDEF are compiled and the statements following $ELSE are ignored.

$DEFINE Prototype X	/* define Prototype*/

$IFDEF Prototype

pin 1	= memreq;	/* memory request on  */

/* pin 1 of prototype*/

pin 2	= ioreq;	/* I/O request on*/

/* pin 2 of prototype*/

$ELSE

pin 1	= ioreq;	/* I/O request on*/

/* pin 1 of PCB*/

pin 2	= memreq;	/* memory request on  */

/* pin 2 of PCB*/

$ENDIF

To compile the statements following $ELSE, remove the definition of Prototype.


$REPEAT

This command is similar to the FOR statement in C language and DO statements in FORTRAN language. It allows the user to duplicate repeat body by index. The format is as follows:

$REPEAT index=[number1,number2,Énumbern]
repeat body
$REPEND

where n can be any number in the range 0 to 1023

In preprocessing, the repeat body will be duplicated from number1 to numbern. The index number can be written in short form as [number1..numbern] if the number is consecutive. The repeat body can be any CUPL statement. Arithmetic operations can be performed in the repeat body. The arithmetic expression must be enclosed by braces { }.

For example, design a three to eight decoder.

FIELD sel = [in2..0]
$REPEAT i = [0..7]
!out{i} = sel:'h'{i} & enable;
$REPEND

Where index variable i goes from 0 to 7, so the statement out{i} = sel:'h'{i} &enable; will be repeated during preprocessing and create the following statements:

FIELD sel = [in2..0];
!out0 = sel:'h'0 & enable;
!out1 = sel:'h'1 & enable;
!out2 = sel:'h'2 & enable;
!out3 = sel:'h'3 & enable;
!out4 = sel:'h'4 & enable;
!out5 = sel:'h'5 & enable;
!out6 = sel:'h'6 & enable;
!out7 = sel:'h'7 & enable;

The following example shows how the arithmetic operation addition (+) and modulus (%) are used in the repeat body.

/*Design a five bit counter with a control signal advance.
If advance is high, counter is increased by one.*/

FIELD count[out4..0]
SEQUENCE count {
$REPEAT i = [0..31]
PRESENT S{i}
IF advance & !reset NEXT
S{(i+1)%(32)};
IF reset NEXT S{0};
DEFAULT NEXT S{i};
$REPEND
}


repend
$REPEND

This command ends a repeat body that was started with $REPEAT. The format is as follows:

$REPEND

The statements following the $REPEND command are compiled in the same way as the statements preceding the $REPEAT command. For each $REPEAT command, an associated $REPEND command must be used.


$MACRO

This command creates user-defined macros. The format is as follows:

$MACRO name argument1 argument2...argumentn
macro function body
$MEND

The macro function body will not be compiled until the macro name is called. The function is called by stating function name and passing the parameters to the function.

Like the $REPEAT command, the arithmetic operation can be used inside the macro function body and must be enclosed in braces.

The following example illustrates how to use the $MACRO command.

Use the $MACRO command to define a decoder function with an arbitrary number of bits. This example places the macro definition and call in the same file.

$MACRO decoder bits  MY_X  MY_Y MY_enable;
FIELD select = [MY_Y{bits-1}..0];
$REPEAT i = [0..{2**(bits-1)}]
!MY_X{i} = select:'h'{i} & MY_enable;
$REPEND
$MEND
É/* Other statements */

decoder(3, out, in, enable);  /*macro function call*/

Calling function decoder will create the following statements by macro expansion.

FIELD sel = [in2..0];
!out0 = sel:'h'0 & enable;
!out1 = sel:'h'1 & enable;
!out2 = sel:'h'2 & enable;
!out3 = sel:'h'3 & enable;
!out4 = sel:'h'4 & enable;
!out5 = sel:'h'5 & enable;
!out6 = sel:'h'6 & enable;
!out7 = sel:'h'7 & enable;

When macros are called, the keyword NC is used to represent no connection. Because NC is a keyword, the letters NC should not be used as a variable elsewhere in CUPL.

A macro expansion file can be created by using the -e flad when compiling the PLD file. CUPL will create an expanded macro file with the same name as the PLD file, with the extension .mx.

The macro definition can be stored in a separate file with a .m extension. Using the $INCLUDE command, specify the file. All the macro functions in that file will then be accessible. The following example shows the macro definition and calling statement stored in different files.

The macro definition of decoder is stored in the file macrolib.m

$INCLUDE macrolib.m /*specify the macro library */
É/* other statements */
decoder(4, out, in enable);
É/* other statements */

More examples can be found in the example files provided on the WINCUPL diskettes.


$MEND

This command ends a macro function body started with $MACRO. The format is as follows:

$MEND

The statements following the $MEND command are compiled in the same way as the statements preceding the $MACRO command. For each $MACRO command, an associated $MEND command.must be used.


Logical Operator

CUPL supports the four standard logical operators used for boolean expressions. Following table lists these operators and their order of precedence, from highest to lowest.

Precedence of Logical Operators

Operator	Example	Description	Precedence

!	!A	NOT	1
&	A & B	AND	2
#	A # B	OR	3
$	A $ B	XOR	4


index variable

Index Variable Bit Fields and Equality

Indexed variables, field statements and the range function operate with each other in tight union. This section will attempt to illustrate this relationship.

Indexed variables can be used as an easy way to declare multiple variables with few actual lines of code.

For example

Pin [2..4] = [AD0..2];

expands to:

Pin 2 = AD0;
Pin 3 = AD1;
Pin 4 = AD2;

The Field statement is used to group a set of related signals into one element. It works by using a 32 bit field where each bit in the field represents one of the members of the field. If there are less than 32 members then the extra bits are ignored. For example:

Pin 2 = VAR_A;
Pin 3 = VAR_B;
Pin 4 = VAR_C;
Pin 15 = ROM_SEL;
FIELD ADDR = [VAR_A,VAR_B,VAR_C];

The following figure shows how the variables VAR_A, VAR_B and VAR_C map into the bit field.

xxxxxxxxxxxxxxxxxxxxxxxxxxxxx VAR_A VAR_B VAR_C

                                                      bit2        bit1      bit0

Now suppose that we had an output as follows:

ROM_SEL = ADDR:3;

The contents of the bit field for this equation would be as follows:

XXXXXXXXXXXXXXXXXXXXXXXXXXXXX011

This would result in the following equations:

ROM_SEL = !VAR_A & VAR_B & VAR_C;

When using indexed variables, the internal representation changes slightly. The index number of the variable determines its position in the bit field. Therefore, VAR0 always resides in bit position 0 regardless of the declaration of the field. The two following declarations both have the identical internal representation.

field ADDR = [VAR0, VAR1, VAR2];
field ADDR = [VAR2, VAR1, VAR0];

xxxxxxxxxxxxxxxxxxxxxxxxxxxxx VAR_2 VAR_1 VAR_0

                                                      bit2        bit1      bit0

 Bit field representation with indexed variables

Now suppose that we had an output as follows:

ROM_SEL = ADDR:3;

The contents of the bit field for this equation would be as follows:

XXXXXXXXXXXXXXXXXXXXXXXXXXXXX011

This would result in the following equations:

ROM_SEL = !VAR2 & VAR1 & VAR0;

If we take a set of variables that use a higher index we can see that the way indexed variables are handled may affect the output differently than we expect. If the variables used are VAR17, VAR18 and VAR19 then the bit map changes accordingly. The equivalence with 3 now does not work because 3 only maps into bits 0, 1 and 2. What needs to be done is to add zeroes to move the desired equivalence up to the desired range.

Now suppose that we had an output as follows:

FIELD ADDR = [VAR18, VAR17, VAR16];
ROM_SEL = ADDR:3;

The variables would map into the bit field ADDR as follows:

xxxxxxxxxxxxx VAR18 VAR17 VAR 16 xxxxxxxxxxxxxxxx

                          bit18     bit17      bit16

Bit field representation with indexed variables not starting at 0

If we attempt to apply an equivalence of three to this bit field, the bits will not match correctly.

The following line shows how the constant three maps onto the bit field.

XXXXXXXXXXXXXXXXXXXXXXXXXXXXX011

Notice that the significant bits in the above equivalence does not map over the bits representing the variables. What needs to be done to make this correct is to append enough zeroes to the end of the constant so that it represents what we truly want.

ROM_SEL = ADDR:30000;

This will now produce the correct results since the bit map from this constant is as follows:

XXXXXXXXXXXXX0110000000000000000

ROM_SEL = !VAR18 & VAR17 & VAR16;


Extension

Extensions can be added to variable names to indicate specific functions associated with the major nodes inside a programmable device, including such capabilities as flip-flop description and programmable three-state enables. Following table lists the extensions that are supported by Atmel-CUPL and on which side of the equal sign, (=) L= left, R= Right, they are used. The compiler checks the usage of the extension to determine whether it is valid for the specified device and whether its usage conflicts with some other extension used.

Extensions

Extension	Side Used	Description

.AP	L	Asynchronous preset of flip-flop

.AR	L	Asynchronous reset of flip-flop

.CE	L	CE input of enabled D-CE type flip-flop

.CK	L	Programmable clock of flip-flop

.CKMUX	L	Clock multiplexer selection

.D	L	 D input of D-type flip-flop

.DQ	L	D-input of a D-type input register

.DFB	R	D registered feedback path selection

.INT	L	Buried Combinatorial Feedback

.IO	R	Pin feedback path selection

.J	L	J input of JK-type output flip-flop

.K	L	K input of JK-type output flip-flop

.L	L	D input of transparent latch

.LQ	L	D-input of a transparent input latch

.LE	L	Programmable latch enable

.OE	L	Programmable output enable

.R	L	R input of SR-type output flip-flop

.S	L	S input of SR-type output flip-flop

.SP	L	Synchronous preset of flip-flop

.T	L	T input of toggle output flip-flop

.TFB	R	T registered feedback path selection

Each extension provides access to a specific function. For example, to specify an equation for output enable (on a device that has the capability) use the .OE extension. The equation will look as follows:

PIN 2 = A;
PIN 3 = B;
PIN 4 = C;
PIN 15 = VARNAME;
VARNAME.OE = A&B;

For those devices containing bi-directional I/O pins with programmable output enables, CUPL automatically generates the output enable expression according to the usage of the pin. If the variable name is used on the left side of an equation, the pin is assumed to be an output and is assigned binary value 1; that is, the output enable expression is defaulted to the following:

PIN_NAME.OE='b'1;	/* Tri-state buffer	*/
/* Always ON	*/

Those pins that are used only as inputs (that is, the variable name appears only on the right side of an equation) are assigned binary value 0; the output enable expression is defaulted to the following:

PIN_NAME.OE = 'b'0;	/* Tri-state buffer
Always OFF	*/

When the I/O pin is to be used as both an input and output, any new output enable expression that the user specifies overrides the default to enable the tri-state buffer at the desired time.

When using a JK or SR-type flip-flop, an equation must be written for both the J and K (or S and R) inputs. If the design does not require an equation for one of the inputs, use the following construct to turn off the input:

COUNT0.J='b'0 ;	/* J input not used	*/

Control functions such as asynchronous resets and presets are commonly connected to a group (or all) of the registers in a device. When an equation is written for one of these control functions, it is actually being written for all of the registers in the group. For documentation purposes, CUPL checks for the presence of such an equation for each register in the group and generates a warning message for any member of the group that does not have an identical equation. If all the control functions for a given group are defined with different equations, the compiler will generate an error since it cannot decide which equation is the correct one. Remember that this is a device specific issue and it is a good idea to understand the capability of the device being used.


Truth Table

CUPL provides the TABLE keyword to create truth tables. The format for using TABLE is as follows:

TABLE var_list_1 => var_list_2  {

input_n => output_n ;
.
.
input_n => output_n ;
}

where

var_list_1 defines the input variables.

var_list_2 defines the output variables.

input_n is a decoded value (hex by default) or a list of decoded values of var_list_1.

output_n is a decoded value (hex by default) of var_list_2.

{ } are braces to begin and end the assignment block.

=> specifies a one-to-one assignment between variable lists, and between input and output numbers.

First, define relevant input and output variable lists, and then specify one-to-one assignments between decoded values of the input and output variable lists. Don't-care values are supported for the input decode value, but not for the output decode value.

A list of input values can be specified to make multiple assignments in a single statement. The following example describes a simple hex-to-BCD code converter:

FIELD  input = [in3..0] ;

FIELD  output = [out4..0] ;

TABLE  input => output {

0=>00;	1=>01;	2=>02;	3=>03;

4=>04;	5=>05;	6=>06;	7=>07;

8=>08;	9=>09;	A=>10;	B=>11;

C=>12;	D=>13;	E=>14;	F=>15;

}


State Machine

The CUPL state-machine model uses six components: inputs, combinatorial logic, storage registers, state bits, registered outputs, and non-registered outputs.

Inputs - are signals entering the device that originate in some other device.

Combinatorial Logic - is any combination of logic gates (usually AND-OR) that produces an output signal that is valid Tpd (propagation delay time) nsec after any of the signals that drive these gates changes. Tpd is the delay between the initiation of an input or feedback event and the occurrence of a non-registered output.

State Bits - are storage register outputs that are fed back to drive the combinatorial logic. They contain the present-state information.

Storage Registers - are any flip-flop elements that receive their inputs from the state machine's combinatorial logic. Some registers are used for state bits: others are used for registered outputs. The registered output is valid Tco (clock to out time) nsec after the clock pulse occurs. Tco is the time delay between the initiation of a clock signal and the occurrence of a valid flip-flop output.

For the system to operate properly, the PLDs requirements for setup and hold times must be met. For most PLDs, the setup time (Tsu) usually includes both the propagation delay of the combinatorial logic and the actual setup time of the flip-flops. Tsu is the time it takes for the result of either feedback or an input event to appear at the input to a flip-flop. A subsequent clock input cannot be applied until this result becomes valid at the flip-flop's input. The flip-flops can be either D, D-CE, J- K, S-R, or T types.

Non-registered Outputs - are outputs that come directly from the combinatorial logic gates. They may be functions of the state bits and the input signals (and have asynchronous timing), or they may be purely dependent on the current state-bit values, in which case they become valid Tco + Tpd nsec after an active clock edge occurs.

Registered Outputs - are outputs that come from the storage registers but are not included in the actual state-bit field (that is, a bit field composed of all the state bits). State- machine theory requires that the setting or resetting of these registered outputs depends on the transition from a present state to a next state. This allows a registered output to be either set or reset in a given state depending upon how the machine came to be in that state. Thus, a registered output can assume a hold operation mode. In the hold mode, the registered output will remain at its last value as long as the current state transition does not specify an operation on that registered output.

Syntax

To implement the state machine model, CUPL supplies a syntax that allows the describing of any function in the state machine.

The SEQUENCE keyword identifies the outputs of a state machine and is followed by statements that define the function of the state machine. The format for the SEQUENCE syntax is as follows:

SEQUENCE state_var_list {
PRESENT  state_n0 statements ;
.
.
.
PRESENT  state_nn statements ;
}

where

state_var_list is a list of the state bit variables used in the state machine block. The variable list can be represented by a field variable.

state_n is the state number and is a decoded value of the state_variable_list and must be unique for each PRESENT statement.

statements are any of the conditional, next, or output statements described in the following subsections of this section.

; is a semicolon used to mark the end of a statement.

{  } are braces to mark the beginning and end of the state machine description.

Symbolic names defined with the $DEFINE command may be used to represent state_numbers.

The SEQUENCE keyword causes the storage registers and registered output types generated to be the default type for the target device. For example, by using the SEQUENCE keyword in a design with a P16V8 target device, the state storage registers and registered outputs will be generated as D-type flip-flops.

The storage registers for certain devices can be programmed as more than one type. In the case of the Atmel ATV750B or ATV2500B they can be either D or T type flip-flops. By default, using the SEQUENCE statement in aATV750B or ATV2500B design will cause the state storage register and registered output equations to be generated using D type flip-flops. To override this default, the SEQUENCET keyword would be used in place of the SEQUENCE keyword. This would cause the state register and registered output equations to be generated using T-type flip-flops. For state-machine which represent counters usign T-type flip-flops  can significantly reduce the number of product term generated by CUPL to implement the state machine equations.

Along with the SEQUENCE and SEQUENCET keywords are the SEQUENCEJK, SEQUENCERS, and SEQUENCED keywords. Respectively, they cause the state register and registered output equations to be generated using J-K, S-R, and D-type flip-flops.

The subsections that follow describe the types of statements that can be written in the state-machine syntax. Statements use the IF, NEXT, OUT and DEFAULT keywords.

Unconditional NEXT Statement

This statement describes the transition from the present state to a specified next state. The format is:

PRESENT state_n

NEXT  state_n ;

where

state_n is a decoded value  of the state bit variables that are the output of the state machine.

Conditional NEXT Statement

This statement describes the transition from the present state to a next state if the conditions in a specified input expression are met. The format is as follows.

PRESENT state_n
IF  expr  NEXT  state_n;
.
.
.
IF  expr  NEXT  state_n;
[DEFAULT  NEXT state_n;]

where

state_n is a decoded value of the state bit variables that are the output of the state machine.

expr is any valid expression (see the subtopic, Expressions in this chapter).

; is a semicolon used to mark the end of a statement.

Unconditional Synchronous Output

This statement describes a transition from the present state to a next state, specifies a variable for the registered (synchronous) outputs associated with the transition, and defines whether the variable is logically asserted. The format is as follows:

PRESENT state_n

NEXT state_n  OUT [!]var... OUT [!]var;

where

state_n is a decoded value (default hex) of the state bit variables that are the output of the state machine.

var is a variable name declared in the pin declarations. It is not a variable from the SEQUENCE state_var_list.

! is the complement operator; use it to logically negate the variable, or omit it to logically assert the variable.

; is a semicolon used to mark the end of a statement.

Conditional Synchronous Output Statement

This statement describes a transition from the present state to a next state, specifies a variable for the registered (synchronous) outputs associated with the transition, and defines whether the variable is logically asserted if the conditions specified in an input expression are met. The format is as follows:

PRESENT state_n

IF expr NEXT state_n OUT [!]var...OUT [!] var;

        .

        .

IF expr NEXT state_n OUT [!]var...OUT [!]var;

[ [DEFAULT] NEXT state_n OUT [!]var;]

where

state_n is a decoded value (default hex) of the state bit variables that are the output of the state machine.

var is a variable name declared in the pin declarations. It is not a variable from the SEQUENCE state_variable_list.

! is the complement operator; use it to logically negate the variable, or omit it to logically assert the variable.

; is a semicolon used to mark the end of a statement.

expr is any valid expression.

Unconditional Asynchronous Output Statement

This statement specifies variables for the non-registered (asynchronous) outputs associated with a given present state, and defines when the variable is logically asserted. The format is as follows:

PRESENT state_n

OUT  var  ...  OUT  var ;

where:

state_n is a decoded value (default hex) of the state bit variables that are the output of the state machine.

var is a variable name declared in the pin declarations. It is not a variable from the SEQUENCE state_var_list.

; is a semicolon used to mark the end of a statement.

Conditional Asynchronous Output Statement

This statement specifies variables for the non-registered (asynchronous) outputs associated with a given present state, and defines when the variables are logically asserted, if the conditions in an input expression are met. The format is as follows:

PRESENT state_n

IF  expr  OUT  var ... OUT var;

            .

 	            .

IF  expr  OUT  var ... OUT var;

[DEFAULT   OUT  var ... OUT var;]

where

state_n is a decoded value (default hex) of the state bit variables that are the output of the state machine.

var is a variable name declared in the pin declarations. It is not a variable from the SEQUENCE statement.

expr is any valid expression.

; is a semicolon used to mark the end of a statement.


CUPLX error messages

0001cx could not open: filename

Fatal. CUPLX cannot continue because of the failure to open the indicated file. Be sure the file exists if it is an input.

0002cx could not execute program: program name

Fatal. CUPLX is unable to perform the next step in the compilation.  Be sure that all of the CUPL program files exist on the same directory or disk.

0003cx no label given for command

Error. One of the preprocessor commands, $DEFINE, $UNDEF, $IFDEF, or $IFNDEF, was used without a succeeding label.

0004cx already defined: label

Error. The label was previously defined using $DEFINE. To redefine the label, first use $UNDEF to undefine the label, and then use $DEFINE to redefine it.

0005cx string error

Fatal. All preprocessor label string space has been used.

0006cx $else without $ifdef

Error. An $ELSE preprocessor command was used without being preceded by an $IFDEF or $IFNDEF command.

0007cx $endif without $ifdef

Error. An $ENDIF preprocessor command was used without being preceded by an $IFDEF or $IFNDEF command.

0008cx $ifdef nesting too deep

Error. The level of $IFDEF nesting exceeded twelve.

0009cx missing $endif

Error. An $IFDEF preprocessor command was used without being succeeded by an $ENDIF command.

0010cx invalid preprocessor command: $command

Error. The preprocessor command is unknown. Refer to Preprocessor Commands in Chapter 2 for a list of valid commands.

0011cx disk write error: filename

Fatal. CUPLX encountered an I/O error trying to write the indicated file. This error usually occurs when there is insufficient disk space.

0012cx out of memory: condition

Fatal. CUPLX has used all the available RAM memory allocated by the operating system.

0013cx illegal character: hex value

Error. CUPLX has encountered an illegal ASCII value in the source file. Make sure the file was created in nondocument mode on the word processor. This error can also be caused by files which were created over a serial modem upload/download link.

0014cx unexpected symbol:symbol

Fatal. CUPLX encountered a symbol that it was not expecting. This occurs when certain symbols are expected in a particular order and are either incorrect, misplaced or misspelled.

0015cx Repeat nesting too deep

Fatal. The level of Repeat nesting exceeded two.

0016cx duplicate Macro function name:function

Error. The Macro function name has already been previously defined. A duplicate Macro name will cause confusion when they are called.

0017cx missing Macro name

Fatal. A Macro was defined without a name. This macro will never be accessed.

0018cx incorrect number of parameters

Fatal. The number of parameters defined in the Macro function did not equal the number of parameters in the macro call. All parameters defined in the Macro function must be defined in the Macro call.

0019cx out of range

Fatal. The index number exceeded 1023. Valid index numbers are 0 - 1023.

0020cx internal stack overflow

Fatal. A mathematical expression was too complex for CUPLX to handle. The expression can be reduced by eliminating as many parenthetical expressions as possible. Expressions are evaluated from left to right using standard precedence. The user should take advantage of this.

0021cx expression contains undefined symbol:symbol

Fatal. A symbol appearing in the expression has not been defined in the source file or predefined by CUPL.

0022cx invalid library access key

Fatal. The version of CUPLX is not compatible with the version of the device library file. This occurs when either CUPLX or the device library, but not both, has been updated.

0023cx invalid library interface

Fatal. Either the device library was not created using the CUPL library manager, CBLD, or CUPLX and the device library are not compatible.

0024cx bad library file: library

Fatal. Either the device library does not exist or the contents of the device library have been damaged.

0025cx unexpected end-of-file

Fatal. CUPLX has unexpectedly reachedx the end-of-file.

0026cx reached end-of-file before ending comment

Fatal. CUPLX detected that acomment was not terminated before reaching the end-of-file. The beginning of the comment can be found by searching for the last occurrence of /* in the PLD file.

0027cx invalid syntax for preprocessor  command: $command

Fatal. One of the preporcessor commands, $REPEAT or $MACRO, has been used improperly. The command syntax contains unexpected symbols.

10xxcx program error: specifics

Fatal. An operating system interface problem is suspected. Contact Logical Devices customer support.


CUPLA error message

0001ca could not open: filename

Fatal. CUPLA cannot continue because of the failure to open the indicated file. Be sure the file exists if it is an input.

0002ca invalid number: number

Error. Either the number is used improperly, or a previous syntax error caused the number to be used improperly.

0003ca invalid library access key

Fatal. The version of CUPLA is not compatible with the version of the device library file. This occurs when either CUPLA or the device library, but not both, has been updated.

0004ca invalid library interface

Fatal. Either the device library was not created using the CUPL library manager, CBLD, or CUPLA and the device library are not compatible.

0005ca bad library file: library

Fatal. Either the device library does not exist or the contents of the device library have been damaged.

0006ca device not in library: device

Fatal. Either the specified target device does not exist or an entry has not been made in the device library for the device.

0007ca invalid syntax: symbol

Error. Either the symbol is used improperly, or a previous syntax error caused the symbol to be used improperly.

0008ca too many errors

Fatal. CUPLA has encountered more than 30 errors.

0009ca missing: symbol

Error. The missing symbol is required to make the specified statement valid.

0010ca vector too wide

Fatal. A variable list has more than 50 members.

0011ca expression already assigned to: variable

Error. The variable (either an intermediate or output variable) was previously assigned an expression. Use APPEND to make multiple expression assignments for the same variable.

0012ca vector size mismatch

Error. The number of members in the variable list on the left side of the equation does not match the number of variables on the right side.

0013ca undefined function: function

Error. The variable name used as a function reference has no corresponding function definition. Functions must be defined before they can be referenced.

0014ca variable already declared: variable

Error. The variable which was previously assigned an expression cannot be reassigned.

0015ca out of memory: condition

Fatal. CUPLA has used all available RAM memory which has been allocated by the operating system. Decrease the number of intermediate variables, fields, or numbers in order to reduce the size of the symbol table.

Note

This error is not a result of insufficient product terms in the device to implement a particular expression.

0016ca invalid number of function arguments: number

Error. The user has attempted to pass an incorrect number of arguments to the user-defined function. The number of arguments for the function reference does not match the number in the function definition.

0017ca disk write error: filename

Fatal. CUPLA encountered an I/O error trying to write the indicated file. This error usually occurs when there is insufficient disk space.

0018ca intermediate var not assigned an expression: variable

Error. The intermediate variable was used as an input in an expression without having been assigned an expression. This error often occurs when a pin or intermediate variable in a logic expression is misspelled.

0019ca indexed and non-indexed vars in range or match expression

Warning. A list (or field variable) in a range or match expression contains both indexed (variable names ending in a number) and nonindexed variables. This type of operation cannot produce the expected results because of inability to hold relative bit positions in the field. It is recommended to use all non-indexed variables in a field for portability to future versions of CUPL.

0020ca index too large for range or match operation

Error. The index of a variable in a list or field exceeds the range or match values.

0021ca header item already declared

Error. One of the header statements was duplicated.

0022ca missing header item(s)

Warning. At least one of the header statements is missing.

0023ca invalid range arguments: always true (in range)

Error. A range has been specified which will always be true and is therefore not an actual range. CUPLA attempts to minimize range functions and does not allow a NULL range such as this. This happens with ranges such as [0000..FFFF] for a 16-bit address. This error can also be given if non-indexed list variables are used in a range expression.

0024ca range or match number larger than variable list

Warning. The range or match number exceeds the width of the bit field it is being applied to. Values exceeding the width of the bit field will be ignored.

0025ca range minimization error

Error. The range reduces to always false, that is, none of the bits in the range are active.

0026ca invalid table statement

Error. Input numbers cannot be mapped into more than one output number.

0027ca invalid present state number

Error. The present state number specified is not valid. This error can occur whenever the present state has not been properly defined as a number using the $DEFINE command.

0028ca invalid next state number

Error. The next state number specified is not valid. This error can occur whenever the next state has not been properly defined as a number using the $DEFINE command.

0029ca invalid flip-flop type for sequence statement: type

Error. The flip-flop type for this device cannot be used for building the requested sequential state machine.

0030ca intermediate dependent on itself: variable

Error. The intermediate variable was used in the expression defining the same intermediate variable. This error often occurs when an intermediate variable is misspelled or an output pin expression is being defined using feedback without declaring the output variable as a pin.

0031ca invalid minimization level: level

Error. The minimization level specified is invalid. Refer to Running CUPL in Chapter 2 for valid minimization levels.

0032ca invalid next state: hex number

Error. The next state value is invalid. This error can occur whenever the next state has not been properly defined as a number using the $DEFINE command or has not been identified as a present state using the present command.

0033ca multiple asynchronous defaults for state: hex number

Error. By definition, only one asynchronous default expression can be assigned for any one state. The resulting expression is the complement of all previous conditional (if) asynchronous expressions.

0034ca multiple synchronous defaults for state: hex number

Error. By definition, only one synchronous default expression can be assigned for any one state. The resulting expression is the complement of all previous conditional (if) synchronous expressions.

0035ca multiple unconditional statements for state: hex number

Error. By definition, only one unconditional synchronous statement can be given for any one state.

0036ca device does not support synchronous state machines

Fatal. The device specified for compilation cannot be used with the sequence statement since it does not support registered operations.

0037ca duplicate present state: hex number

Error. The present state number was identified in more than one PRESENT command. This can occur when symbolic state names are used to refer to states, but the $DEFINE command, used to define states, assigned the same number to more than one symbolic name.

0038ca target device not specified

Fatal. The user did not specify a target device on the command line and the source file did not contain a DEVICE assignment in the header information.

0039ca line exceeds maximum length

Error. The statement is greater than 256 characters long. Break the line up into shorter statements.

0040ca invalid or duplicate header name: name

Fatal. The NAME field in the header information must not be NULL.  When more than one device is being defined in a logic description file, the NAME field in the header information must be unique.

0041ca don't care(s) not allowed for decimal number, treated as 0

Warning. Don't-care values, X, are valid only for binary, octal, and hexadecimal numbers.

0042ca range or match list completely don't cared, decoded as 0

Warning. The variable list in a range or match operation has been completley don't-cared, leaving an empty variable list.  The empty variable list will be decoded into a 0.

0043ca invalid GROUP name:  variable name

Fatal. The GROUP name must contain the keyword BLOCK_ followed by variable name. Ex. GROUP BLOCK_A=[X,Y]; where A is the variable name.

0044ca unexpected end-of-file

Fatal. CUPLA has unexpectedly reached the end-of-file.

0045ca ireached end-of=file before ending comment

Fatal. CUPLA detected that a comment was not terminated before reaching the end-of-file. The beginning of the comment can be found by searching for last occurence of /* in the PLD file.

0046ca invalid demorgan level:  symbol

Error. The valid level is between 0 to 2. Symbol is the variable defined in the DEMORGAN statement.

0047ca compare different size vectors:  symbol

Fatal. The size of two vectors in the compare operator are different. Symbol ois the left hand side variable name.

0048ca fixed polarity device, reset demorgan level to 0:  symbol

Warn. ignore the demorgan statement in a fixed polarity device.

0049ca unknown declare tyoe:  symbol

Fatal. Unsupported declare type. Symbol is the type name.

10xxca program error: specifics

Fatal. An operating system interface problem is suspected. Contact Logical Devices, customer support.


CUPLB error messages

0001cb could not open: filename

Fatal. CUPLB cannot continue because of the failure to open the indicated file. Be sure the file exists if it is an input.

0002cb could not execute program: program name

Fatal. CUPLB is unable to perform the next step in the compilation.  Be sure that all of the CUPL program files exist on the same directory or disk.

0003cb invalid file: filename

Warning. The file was not created by the current version of CUPL.

0004cb missing or mismatched parentheses:

Error. The number of open parentheses [(] and close parentheses [)] in the specified statement does not match.

0005cb invalid library access key

Fatal. The version of CUPLB is not compatible with the version of the device library file. This occurs when either CUPLB or the device library, but not both, has been updated.

0006cb invalid library interface

Fatal. Either the device library was not created using the CUPL library manager, CBLD, or CUPLB and the device library are not compatible.

0007cb bad library file: library

Fatal. Either the device library does not exist or the contents of the device library have been damaged.

0008cb device not in library: device

Fatal. Either the specified target device does not exist or an entry has not been made in the device library for the device.

0009cb pin/node number redeclared: variable

Error. The same pin number or variable name was used more than once in a pin declaration statement.

0010cb pin/node number invalid output: variable

Error. The variable being assigned an output expression was previously declared for an input-only pin.

0011cb unknown extension: extension

Error. The extension is unknown or invalid for the particular device.  Refer to Extensions in Chapter 2 for a list of valid extensions.  Check to make sure the device has the capability required.

0012cb pin/node number invalid usage: variable

Fatal. The pin number assigned to the variable is invalid for the target device specified.

0013cb pin/node number invalid output extension or usage: variable

Error. Either the extension is used improperly or it is not valid for the assigned pin/node.

0014cb invalid input: variable or pin/node number  invalid input: variable

Error. The variable used as an input was previously assigned to an output that is neither bidirectional nor feeds back into the input array.

0015cb device not yet fully supported: device

Fatal. There is an entry for the device in the device library, but the device is not fully supported by the current version of CUPL.

0016cb no expression assigned to: variable

Warning. The variable requires an output expression assignment. This warning message is commonly given when all outputs in a bank have the same capability (reset, preset, and so on) and not all the variables have been assigned the same expression. It is given to remind the user that all outputs will be affected.

Note

This warning may be suppressed by assigning the variable to 'b'0 or 'b'1 as appropriate.

0017cb out of memory: conditions

Fatal. CUPLB has used all available RAM memory that has been allocated by the operating system, typically as a result of performing a DeMorgan or expansion operation on a large expression. If using fixed polarity devices, check to make sure that the pin variable declaration matches the polarity of the device. Also check whether an intermediate variable which has been expressed in sum-of-product form is being complemented.

Note

This error does not result from insufficient product terms in the device to implement a particular expression.

0018cb missing flip-flop expression for: variable

Error. The matching flip-flop expression for a J-K or S-R type flip-flop is missing. Both inputs must have expressions assigned to them. An input may be assigned to 'b'0 or 'b'1 as appropriate.

0019cb DeMorgan's theorem invoked for: variable

Warning. DeMorgan's Theorem has been applied to the expression assigned to the variable. Unlike D- or T-type flip-flops, meaningful results are not guaranteed when a DeMorgan equivalent expression is applied to the logic input.

0020cb invalid mix of banked outputs: variable

Error. All outputs in a banked group must be used in the same manner.  An attempt was made to mix registered and nonregistered output types.

0021cb no expression allowed for: variable

Error. Logic expressions are not allowed for reset and preset nodes when the output has been specified as asynchronous. CUPL will generate the proper defaults.

0022cb pin/node number conflicting input architectures: variable

Error. A fuse-assigned input architecture must be used consistently in all expressions. An attempt was made to specify both fuse options in different expressions.

0023cb disk write error: filename

Fatal. CUPLB encountered an I/O error trying to write the indicated file. This error usually occurs when there is insufficient disk space.

0024cb output defined for node which does not exist: "variable"

Error. Variable is defined for a pin or node number which does not exist.

0025cb output mutually excluded by previous output: variable

Error. Variable usage is mutually excluded by a previous usage or other output. A shared product term or terms has been defined more than once.

0026cb disk read error, unexpected end of file: filename

Fatal. CUPLB encountered an I/O error trying to read the indicated file. This error usually occurs when the file is being read from damaged media.

10xxcb program error: specifics

Fatal. An operating system interface problem is suspected. Contact Logical Devices  customer support.


CUPLM error messages

0001cm could not open: filename

Fatal. CUPLM cannot continue because of the failure to open the indicated file. Be sure the file exists if it is an input.

0002cm could not execute program: program name

Fatal. CUPLM is unable to perform the next step in the compilation.  Be sure that all of the CUPL program files exist on the same directory or disk.

0003cm invalid file: filename

Warning. The file was not created by the current version of CUPL.

0004cm out of memory: conditions

Fatal. CUPLM has used all available RAM memory which has been allocated by the operating system while performing logic reduction.

Note

This error does not result from insufficient product terms in the device to implement a particular expression.

0005cm disk write error: filename

Fatal. CUPLM encountered an I/O error trying to write the indicated file. This error usually occurs when there is insufficient disk space.

0006cm invalid library access key

Fatal. The version of CUPLM is not compatible with the version of the device library. This occurs when either CUPLM or the device library, but not both, has been updated.

0007cm invalid library interface

Fatal. Either the device library was not created using the CUPL library manager, CBLD or CUPLM and the device library are not compatible.

0008cm bad library file: library

Fatal. Either the device library does not exist or the contents of the device library have been damaged.

0009cm device is not in library: device

Fatal. Either the specified target device does not exist or an entry has not been made in the device libary for the device.

00010cm design too complex for this minimization level

Fatal. CUPLM has exceeded the array size allowed on this machine while reducing a particular expression. Specify a more efficient minimization level.

00011cm disk read error, unexpected end of file: filename

Fatal. CUPLM encountered an I/O error trying to read the indicated file. This error usually occurs when the file is being read from damaged media.

10xxcm program error: specifics

Fatal. An operating system interface problem is suspected. Contact LDI customer support.


CUPLC error messages

0001cc could not open: filename

Fatal. CUPLC cannot continue because of the failure to open the indicated file. Be sure the file exists if it is an input.

0002cc invalid file: filename

Warning. The file was not created by the current version of CUPL.

0003cc invalid library access key

Fatal. The version of CUPLC is not compatible with the version of the device library. This occurs when either CUPLC or the device library, but not both, has been updated.

0004cc invalid library interface

Fatal. Either the device library was not created using the CUPL library manager, CBLD, or CUPLC and the device library are not compatible.

0005cc bad library file: library

Fatal. Either the device library does not exist or the contents of the device library have been damaged.

0006cc excessive number of product terms: variable

Error. The number of product terms needed to implement the logic expression for the given variable exceeds the capacity of the output pin for which it was declared.

0007cc invalid download format(s)

Warning. At least one of the download formats specified is not available for the target device. For example, the HL download format is not available for PALs or PROMs.

0008cc pin can not be used as input: variable

Error. The pin to which the variable is assigned provides no input or feedback capability.

0009cc header name undefined, using no_name

Error. The NAME field in the header information is missing. Since CUPLC uses this name to generate download files, the desired file will be created as no_name along with the appropriate extension.

0010cc disk write error: filename

Fatal. CUPLC encountered an I/O error trying to write the indicated file. This error usually occurs when there is insufficient disk space.

0011cc out of memory: conditions

Fatal. CUPLC has used all the available RAM memory allocated by the operating system.

Note

This error does not result from insufficient product terms in the device to implement a particular expression.

0012cc disk read error, unexpected end of file: filename

Fatal. CUPLC encountered an I/O error trying to read the indicated file. This error usually occurs when the file is being read from damaged media.

0013cc conflicting usage of pinnode:"variable"

Error. Variable usage is mutually excluded by a previous usage of the pin or pinnode. A shared product term or terms has been defined more than once.

0014cc unknown extension encountered:  extension

Warning. The translation of a CUPL extension into another file format could not be accomplished. The equation is still placed in the new file except the extension has been lost.

0015cc unknown extension encountered:  extension

Warning. The translation of a CUPL extension into another file format could not be accomplished. The equation is still placed in the new file except the extension has been lost.

0016cc exceeded number of expander product terms:

Fatal. Design uses too many expander product terms.

0017cc global feedback in local product term:  symbol

Error. Try to feedback a global singla into a product term which only has local bus.

0022cc unsupported extension

Fatal. The translation of a CUPL extension into another file format could not be accomplished. The translation stopped.

0023cc incorrect number of variables in DECLARE statement:  attribute

Warning. The number of variables in the declare statement does not match the number of pins needed for that attribute.

10xxcc program error: specifics

Fatal. An operating system interface problem is suspected. Contact Logical Devices customer support.


CSIMA error message

0001sa could not open: filename

Fatal. CSIM cannot continue because of the failure to open the indicated file. Be sure the file exists if it is an input.

0002sa invalid number: number

Error. Either the number is used improperly, or a previous syntax error has caused the number to be used improperly.

0003sa invalid file format: filename

Warning. The file was not created by a compatible version of CUPL.

0004sa invalid library access key

Fatal. The version of CSIMA is not compatible with the version of the device library used in the simulation. This occurs when either CSIMA or the device library, but not both, has been updated.

0005sa invalid library interface

Fatal. Either the device library was not created using the CUPL library manager, CBLD, or CSIMA and the device library are not compatible.

0006sa bad library file: library

Fatal. Either the device library does not exist or the contents of the device library have been damaged.

0007sa device not in library: device

Fatal. Either the specified target device does not exist or an entry has not been made in the device library for the device.

0008sa invalid output format: format

Warning. The download format is not available for the target device; for example, the JEDEC download format is not available for PROMS.

0009sa invalid syntax: symbol

Error. Either the symbol is used improperly, or a previous syntax error has caused the symbol to be used improperly.

0010sa expecting device: device

Fatal. The target device is not the same as used when CUPL created the absolute file.

0011sa unknown symbol: symbol

Error. The symbol, used in the order statement, was not previously defined in the CSIM or CUPL source files.

0012sa too many symbols:

Fatal. The number of symbols in the order statement exceeds the number of symbols previously defined in the CSIM and CUPL source files.

0013sa excessive test value value

Error. The test vector value is greater than the maximum possible value defined in the order statement. This error will occur when there are too many test values.

0014sa insufficient test values

Fatal. The test vector value is less than the minimum possible value defined in the order statement. This error will occur when there are too few test values.

0015sa field already defined: field

Error. The field name was previously used in either the CSIM or CUPL source files.

0016sa too many errors

Fatal. CSIM has encountered too many errors to continue.

0017sa missing symbol symbol

Error. CSIM expected a keyword.

0018sa out of memory: condition

Fatal. CSIM has used all the available RAM memory allocated by the operating system.

0019sa user expected (value) for: variable

Error. The test value expected by the user in the .SI file did not match the actual value computed by CSIM.

0020sa unstable output: variable

Error.  The output variable did not have the same test value for two continuous evaluation passes after the maximum twenty passes were attempted. Check the logic equation for an untestable design.

0021sa invalid test value: value

Error. Either the test value is an invalid test vector symbol or the test value is used improperly; that is, a test value of 0 is used for an output.

0022sa bad fault id: jedec number

Error. The JEDEC number, given as the fault ID, is not the address of the beginning of a product term.

0023sa could not read file: filename

Fatal. CSIM could not read from the specified file. This occurs when the contents of the file have been corrupted.

0024sa could not write file: filename

Fatal. CSIM could not write to the specified file. This occurs when the file is write protected or there is no room left on the disk.

0025sa inconsistent header information

Warning. The header information in the CSIM source file does not match the header information in the CUPL source file used to create the absolute file.

0026sa missing header item(s)

Warning. At least one of the header statements is missing.

0027sa old absolute file format for filename

Fatal. The absolute file was created by an incompatible version of CUPL.

0028sa statement too long

Fatal. The statement exceeds 256 characters.

0029sa invalid trace level: number

Error. The trace level must be a decimal number in the range of 0 through 4.

0030sa invalid character: hex value

Error. CSIMA has encountered an illegal ASCII value in the source file. Make sure the file was created in nondocument mode on the word processor. This error can also be caused by files which were created over a serial modem upload/download link.

0031sa disk read error, unexpected end of file: filename

Fatal. CSIMA encountered an I/O error trying to read the indicated file. This error usually occurs when the file is being read from damaged media.

0032sa feedback usage of undefined output:  variable name

Fatal. The variable name does not exist in the ORDER statement and it is being used as input/feedback for another variable. Simulation cannot occur until all relevant variables are defined.

0033sa pin number is undefined for:  variable name

Fatal. When simulating a design in a specified device, CSIM needs to have all the pin numbers defined. The variable name in the PLD file was not assigned a pin number. The PLD file has to be recompiled with all the pin numbers in place.

10xxsa program error: specifies

Fatal. An operating system interface problem is suspected. Contact Logical Devices customer support.


CBLD error message

0001ba invalid syntax: statement line number

Fatal. The specified statement contains a syntax error.

0002ba could not open: filename

Fatal. CBLD cannot continue because of the failure to open the indicated file. Be sure the file exists if it is an input.

0003ba invalid flag: flag

Warning. CBLD will warn that the invalid flag cannot be evaluated, and then continue operation. Invoke CBLD without arguments for a list of valid flags.

0004ba invalid library access key

Warning. The version number of CBLD does not match the version number of the device library. This occurs when either CBLD or the device library, but not both, has been updated. To prevent incompatibility problems, it is important that the version numbers match.

0005ba invalid library interface

Fatal. Either the device library was not created using CBLD, or the library and CBLD have different version numbers causing incompatibility problems.

0006ba bad library file: library

Fatal. Either the device library does not exist or the contents have been damaged.

0007ba device not in library: device

Warning. Either the specified target device does not exist or an entry has not been made in the device library for the device.

0008ba inconsistent library access key

Warning. During a build operation, the target library and a source library have different access keys.

0009ba inconsistent library rev

Warning. During a build operation, the target library and a source library have different revision numbers.

0010ba too many devices for target library: library

Fatal. The device library directory is full.

0011ba device not in library: device

Error. Either the specified device does not exist or an entry has not been made in the device library.

0012ba could not find LIBCUPL in ENVIRONMENT

Fatal. The LIBCUPL assignment has not been made in the ENVIRONMENT.

0013ba too many devices on command line

Error. The user has specified too many devices on the command for CBLD to proceed. The maximum allowable is determined by the command line limit of the operating system.

0014ba disk write error: filename

Fatal. CBLD encountered an I/O error in trying to write the indicated file. This error usually occurs when there is insufficient disk space.

0015ba out of memory: condition

Fatal. CBLD has used all the available RAM memory allocated by the operating system. Check for the existence of print spoolers, RAM disks, or other memory-resident programs which may decrease the amount of memory available to the CUPL application progam.

10xxba program error: specifies

Fatal. An operating system interface problem is suspected. Contact Logical Devices customer support.


CUPLK error message

0001ck could not open: filename

Fatal. CUPL cannot continue because of the failure to open the indicated file. Be sure the file exists if it is an input.

0002ck could not execute program: program name

Fatal. CUPL is unable to perform the next step in the compilation.  Be sure that all of the CUPL program files exist on the same directory or disk.

0003ck could not find PATH in ENVIRONMENT

Fatal. The PATH assignment has not been made in the ENVIRONMENT.

0004ck could not find LIBCUPL in ENVIRONMENT

Fatal. The LIBCUPL assignment has not been made in the ENVIRONMENT.

0005ck could not find program: program name

Fatal. CUPL is unable to locate the CUPL programs using the PATH in the ENVIRONMENT.

0006ck insufficient memory to execute program: filename

Fatal.  Not enough program storage available to load and execute the program. Refer to Chapter 1, Introduction, for the minimum memory requirements for the configuration being used.

0007ck invalid flag: option flag

Fatal. The option flag specified is not one of the allowable compilation flags. Verify proper command line flags and syntax as discussed in Chapter 2, Using CUPL.

0008ck out of memory: condition

Fatal. CUPL has used all available RAM memory which has been allocated by the operating system. Check for the existence of print spoolers, RAM disks, or other memory-resident programs which may decrease the amount of memory available to the CUPL application.

10xxck program error: specifics

Fatal. An operating system interface problem is suspected. Contact Logical Devices, Customer Support.


CSIMK error message

0001sk could not open: filename

Fatal. CSIM cannot continue because of the failure to open the indicated file. Be sure the file exists if it is an input.

0002sk could not execute program: program name

Fatal. CSIM is unable to perform the next step in the simulation.  Be sure that all of the CSIM program files exist on the same directory or disk.

0003sk could not find PATH in ENVIRONMENT

Fatal. The PATH assignment has not been made in the ENVIRONMENT.

0004sk could not find LIBCUPL in ENVIRONMENT

Fatal. The LIBCUPL assignment has not been made in the ENVIRONMENT.

0005sk could not find program: program name

Fatal.  CSIM is unable to locate the CSIM program using the PATH in the ENVIRONMENT.

0006sk insufficient memory to execute program: filename

Fatal. Not enough program storage available to load and execute the program. Refer to the System Overview for the minimum memory requirements for the configuration being used.


Device Node Numbering

A node number listing for Atmel devices is shown below.  The ATF1500A has the same node numbers as the ATF1500. The ATV2500H/L has the same node numbers as the ATV2500B/BQL.
Node numbers for the ATF1508 are the same regardless of package types.

ATV750/B

DIP	Q1 NODE,(Q0 NODE)	PLCC	Q1 NODE,(Q0 NODE)
14	25, (35)	17	29, (39)
15	26, (36)	18	30, (40)
16	27, (37)	19	31, (41)
17	28, (38)	20	32, (42)
18	29, (39)	21	33, (43)
19	30, (40)	23	34, (44)
20	31, (41)	24	35, (45)
21	32, (42)	25	36, (46)
22	33, (43)	26	37, (47)
23	34, (44)	27	38, (48)

ATF1500

PLCC/(TQFP)	Macrocell	Foldback Node	Buried Reg/COM Node
4, (42)	1	45	77
5, (43)	2	46	78
6, (44)	3	47	79
7, (1)	4	48	80
8, 14	5	49	81
9, (3)	6	50	82
11, (5)	7	51	83
12, (6)	8	52	84
13, (7)	9	53	85
14, (8)	10	54	86
16, (10)	11	55	87
17, (11)	12	56	88
18, (12)	13	57	89
19, (13)	14	58	90
20, (14)	15	59	91
21, (15)	16	60	92
41, (35)	17	61	93
40, (34)	18	62	94
39, (33)	19	63	95
38, (32)	20	64	96
37, (31)	21	65	97
36, (30)	22	66	98
34, (28)	23	67	99
33, (27)	24	68	100
32, (26)	25	69	101
31, (25)	26	70	102
29, (23)	27	71	103
28, (22)	28	72	104
27, (21)	29	73	105
26, (20)	30	74	106
25, (19)	31	75	107
24, (18)	32	76	108

ATV2500/B

DIP	Q1 NODE,(Q2 NODE)	PLCC	Q1 NODE,(Q2 NODE)
4	65, (41)	5	69, (45)
5	66, (42)	6	70, (46)
6	67, (43)	7	71, (47)
7	68, (44)	8	72, (48)
8	69, (45)	9	73, (49)
9	70, (46)	10	74, (50)
11	71, (47)	13	75, (51)
12	72, (48)	14	76, (52)
13	73, (49)	15	77, (53)
14	74, (50)	16	78, (54)
15	75, (51)	17	79, (55)
16	76, (52)	18	80, (56)
24	77, (53)	27	81, (57)
25	78, (54)	28	82, (58)
26	79, (55)	29	83, (59)
27	80, (56)	30	84, (60)
28	81, (57)	31	85, (61)
29	82, (58)	32	86, (62)
31	83, (59)	35	87, (63)
32	84, (60)	36	88, (64)
33	85, (61)	37	89, (65)
34	86, (62)	38	90, (66)
35	87, (63)	39	91, (67)
36	88, (64)	40	92, (68)

ATF1508

Note: If you are planning to program the ATF1508 using In-system Programming (ISP) the JTAG port pin are not available as logic inputs. However, logic output may be buried on these macrocells. If you plan to use this pins as logic inputs, program the device on an external device programmer.

	Feedback Node	Foldback Node	Signal Name	Pinout
MC	Number	Number		68-Pin	84-Pin	100-PinQFP	100-pin TQFP	160-PinQFP
128	728	428		65	81	87	85	137
127	727	427		--	--	--		--
126	726	426		--	80	86	84	136
125	725	425		64	79	85	83	135
124	724	424		--	--	--		134
123	723	423		62	77	83	81	132
122	722	422		--	--	--		--
121	No Casout 721	421		--	--	82	80	131
120	720	420		61	76	81	79	130
119	719	419		--	--	--		--
118	718	418		--	75	80	78	129
117	717	417		60	74	79	77	128
116	716	416		--	--	--		123
115	715	415		59	73	78	76	122
114	714	414		--	--	--		--
113	No Casout 713	413		--	--	77	75	121
112	712	412	JTAG TDO pin	57	71	75	73	112
111	711	411		--	--	--		--
110	710	410		--	--	74	72	111
109	709	409		56	70	73	71	110
108	708	408		--	--	--		109
107	707	407		55	69	72	70	108
106	706	406		--	--	--		--
105	No Casout 705	405		--	68	71	69	107
104	704	404		54	67	70	68	106
103	703	403		--	--	--		--
102	702	402		--	--	69	67	105
101	701	401		52	65	67	65	103
100	700	400		--	--	--		102
99	699	399		51	64	66	64	101
98	698	398		--	--	--		--
97	No Casout 697	397		--	63	65	63	100
96	696	396	JTAG TCK pin	50	62	64	62	99
95	695	395		--	--	--		--
94	694	394		--	61	63	61	98
93	693	393		49	60	62	60	97
92	692	392		--	--	--		96
91	691	391		47	58	60	58	94
90	690	390		--	--	--		--
89	No Casout 689	389		--	--	59	57	93
88	688	388		46	57	58	56	92
87	687	387		--	--	--		--
86	686	386		--	56	57	55	91
85	685	385		45	55	56	54	90
84	684	384		--	--	--		89
83	683	383		44	54	55	53	88
82	682	382		--	--	--		--
81	No Casout 681	381		--	--	54	52	80
80	680	380		42	52	52	50	78
79	679	379		--	--	--		--
78	678	378		--	--	51	49	73
77	677	377		41	51	50	48	72
76	676	376		--	--	--		71
75	675	375		40	50	49	47	70
74	674	374		--	--	--		--
73	No Casout 673	373		--	49	48	46	69
72	672	372		39	48	47	45	68
71	671	371		--	--	--		--
70	670	370		--	--	46	44	67
69	669	369		37	46	44	42	65
68	668	368		--	--	--		64
67	667	367		36	45	43	41	63
66	666	366		--	--	--		--
65	665	365		--	44	42	40	62
	Feedback Node	Foldback Node	Signal Name	Pinout
MC	Number	Number		68-Pin	84-Pin	100-PinQFP	100-pin TQFP	160-PinQFP
INPUT	none	none	(OE2/GCLK2)	2	2	92	90	142
INPUT	none	none	(GCLK1)	67	83	89	87	139
INPUT	none	none	(GCLR)	1	1	91	89	141
INPUT	none	none	(OE1)	68	84	90	88	140
1	601	301		--	--	4	2	160
2	602	302		--	--	--		--
3	603	303		10	12	3	1	159
4	604	304		--	--	--		158
5	605	305		9	11	2	100	153
6	606	306		--	10	1	99	152
7	607	307		--	--	--		--
8	No Casout  608	308		8	9	100	98	151
9	609	309		--	--	99	97	150
10	610	310		--	--	--		--
11	611	311		7	8	98	96	149
12	612	312		--	--	--		147
13	613	313		5	6	96	94	146
14	614	314		--	5	95	93	145
15	615	315		--	--	--		--
16	No Casout 616	316		4	4	94	92	144
17	617	317		--	22	16	14	21
18	618	318		--	--	--		--
19	619	319		18	21	15	13	20
20	620	320		--	--	--		19
21	621	321		17	20	14	12	18
22	622	322		--	--	12	10	16
23	623	323		--	--	--		--
24	No Casout 624	324		15	18	11	9	15
25	625	325		--	17	10	8	14
26	626	326		--	--	--		--
27	627	327		14	16	9	7	13
28	628	328		--	--	--		12
29	629	329		13	15	8	6	11
30	630	330		--	--	7	5	10
31	631	331		--	--	--		--
32	No Casout 632	332	JTAG TDI pin	12	14	6	4	9
33	633	333		--	--	27	25	41
34	634	334		--	--	--		--
35	635	335		25	31	26	24	33
36	636	336		--	--	--		32
37	637	337		24	30	25	23	31
38	638	338		--	29	24	22	30
39	639	339		--	--	--		--
40	No Casout 640	340		23	28	23	21	29
41	641	341		--	--	22	20	28
42	642	342		--	--	--		--
43	643	343		22	27	21	19	27
44	644	344		--	--	--		25
45	645	345		20	25	19	17	24
46	646	346		--	24	18	16	23
47	647	347		--	--	--		--
48	No Casout 648	348	JTAG TMS pin	19	23	17	15	22
49	649	349		--	41	39	37	59
50	650	350		--	--	--		--
51	651	351		33	40	38	36	58
52	652	352		--	--	--		57
53	653	353		32	39	37	35	56
54	654	354		--	--	35	33	54
55	655	355		--	--	--		--
56	No Casout 656	356		30	37	34	32	53
57	657	357		--	36	33	31	52
58	658	358		--	--	--		--
59	659	359		29	35	32	30	51
60	660	360		--	--	--		50
61	661	361		28	34	31	29	49
62	662	362		--	--	30	28	48
63	663	363		--	--	--		--
64	No Casout 664	364		27	33	29	27	43


Virtual Device

The virtual device allows the user to create digital designs for programmable logic without regrad to the target architecture. The virtuak device is not a device at all. It is simply a removal of the restrictions by CUPL, allowing the design to contain unlimited product terms and pins. With the virtual device, CUPL allows all register type to be used, The virtual device is useful for determining the resources needed to implement your design.

Output from CUPL by using virtual device

Valid outptu files when using virtual are

DOC

PLA

PDS

LST

MX

ABS.

The following file are not valid format when using virtual device

JED

HEX

Design State Machine using Virtual Device

When designing state machine with the virtual device, you must indicate the register type. CUPL will not default the state bits to any type of register. If a specific register type is not indicated, compilation will still be completed but the resulting equations will not represent a state machine design. The following examples illustrate state machine design with the virtual design.

D Register

SequenceD bits {

   present 'b'0

      default next 'b'1;

   present 'b'1

     default next 'b'0;

}

T Register

SequenceT bits {

   present 'b'0

      default next 'b'1;

   present 'b'1

     default next 'b'0;

}

JK Register

SequenceJK bits {

   present 'b'0

      default next 'b'1;

   present 'b'1

     default next 'b'0;

}

RS Register

SequenceRS bits {

   present 'b'0

      default next 'b'1;

   present 'b'1

     default next 'b'0;

}


key word
CUPL Keywords

APPEND

ASSEMBLY(ASSY)

COMPANY

CONDITION

DATE

DEFAULT

DESIGNER

DEVICE

ELSE

FIELD(FLD)

FORMAT

FUNCTION

FUSE

IF

LOCATION(LOC)

MIN

NAME

NODE

OUT

PARTNO

PIN

PINNODE

PRESENT

REVISION(REV)

SEQUENCE

SEQUENCED

SEQUENCET

SEQUENCEJK

SEQUENCERS

TABLE

PROPERTY

DECLARE

DEMORGAN

REGISTER_SELECT


APPEND

This statement allow multiple expressions to be assigned to a variable. The expression that results from multiple APPEND statements is the logical OR of each individual append statement.If an expression has not already been assigned to the variable, the first APPEND statement is treated as the first assignment.

The syntax for this statement follows:

APPEND [ ! ]var[.ext] = expr ;

where,

! is the complement operator to optionally define the polarity of the variable
var is a single variable or a list of indexed or non-indexed variables in standard list format
.ext is an optional extension that defines the function of the variable
= is the assignment operator
expr is a valid expression
; is a semicolon to mark the end of the statement

Example:

APPEND Y = A0 & A1 ;

APPEND Y = B0 & B1 ;

APPEND Y = C0 & C1 ;

These three statements are equivalent to the following equation:

Y = (A0 & A1) # (B0 & B1) # (C0 & C1) ;


assembly
ASSEMBLY(ASSY)

This PLD source file header item gives the assembly name of number of the PC board on which the PLD will be used. The abbreviation ASSY can be used.

Header Item Requirement: Optional


COMPANY

This PLD source file Header item specifies the companys name for the PLD design. Useful for proper documentation practice for high volume PLD orders.

Header Item Requirement: Optional


CONDITION

This state machine syntax declares an asynchronous conditional output value without referencing any particular state. The variable is logically asserted whenever the expression of DEFAULT condition is met

The syntax for this statement follows:

CONDITION  {
IF expr0 OUT var ;
.
.
IF exprN OUT var ;
}

Where,

expr is any valid expression
var is a variable name declared in the pin declaration. It can also be a list of indexed or non-indexed variables in list notation.
; is a semicolon used to mark the end of the statement.

Example:

The following block of logic desribes a 2 to 4 line decoder. The two data inputs A and B select one of the 4 decoded Y0 through Y3 outputs whenever the enable signal is asserted.

CONDITION  {
IF enable & !B & !A OUT Y0 ;
IF enable & !B & A OUT Y1 ;
IF enable & B & !A OUT Y2 ;
IF enable & B & !A OUT Y3 ;
}

Whenever a statement specified within the condition block is true the appropriate Y0 through Y3 output is asserted. If no statement within this block is true all Y0 through Y1 outputs are de-asserted.


DATE

This PLD source file header item specifies the date when the PLD source  was created

Header Item Requirement: Required


DEFAULT

This state machine syntax indicates the next state from the present state if none of the specified conditional statements in the present state are met.

See Also  State Machine for more information on how to use this statement

NOTE:

Be careful when using this statement. Since it is the complement of all the conditional statements in the state machine description, this statement can generate many product terms for complex state machine descriptions. This can greatly slow CUPL operation.


DESIGNER

This PLD source file header item Specifies the name of the designer who created the source file.

Header Item Requirement: Optional


DEVICE

This is a field in the header section of the PLD source file.  The compiler looks at this field to determine which target device to compile for. If you wish to compile your design for a Virtual Device then the virtual device name will need to be specified. You can list the devices that are supported for your version of CUPL by using the Utility-Device Library command.

Header Item Requirement: Required


ELSE

This compiler directive reverses the state of conditional compilation defined by the $IFDEF or $IFNDEF directives.

For more information:  See Also the $ELSE statement


FIELD

This statement assigns a single variable name to a group of bits. When the FIELD statement is used the compiler generates a single 32-bit field internally. This is used to represent the variables in the bit field.  Each bit represents one member of a bit field. The bit number represents a member of the bit field and is also used by the compiler as an index number for the internal bit field it generates. Different indexed variable or a mixture of non-indexed and indexed variables should not be used with this statement. This will result in the generation of erroneous equations. After the field variable name is assigned in can be used in an expression. The operation specified in the expression is applied to each bit in the group.

See Also Index Variables Bit Fields and Equalityfor more information

Note:

Do not mix indexed, non-indexed variable or differently indexed variables in a field statement. The compiler may produce unexpected results.

The syntax for this statement follows:

FIELD var = [var, var, ..., var] ;

where,

FIELD is a keyword
var is any valid variable name.
[var,var,...,var] is a list of variable name in list notation
= is the assignment operator
; is a semicolon used to mark the end of the statement.

The square brackets must be used to delimit item in a list.

Example:

All of these statements are equivalent.

FIELD ADDRESS = [A7,A6,A5,A4,A3,A2,A1,A0];

or,

FIELD ADDRESS = [A7..0];

or,

FIELD ADDRESS = [A0..7];

Following are examples on how to use field variables in CUPL:

1.  ADDRESS:& =                 A7 & A6 & A5 & A4 & A3 & A2 & A1 & A0;

2.  ADDRESS:# =                  A7 # A6 # A5 # A4 # A3 # A2 # A1 # A0;

3.  ADDRESS:$ =                  A7 $ A6 $ A5 $ A4 $ A3 $ A2 $A1 $ A0;

4.  ADDRESS:hAA =              A7 & !A6 & A5 & !A4 & A3 & !A2 & A1 & !A0;

5.  ADDRESS:B01XXX11X = !A7 & A6 & A2 & A1;

In example five all dont care bits (defined by an X) are removed from the expression. In example four, the value of the field variable is determined by the individual logic values (asserted/de-asserted) of each bit. All bit value are then anded to together to form the complete expression. Examples 1 through 3 show how the AND, OR and XOR operators can be applied to each bit.


FORMAT

This is a field in the header section of the PLD source file.  The characters in this field are used to generate different output formats.  For example, the 'j' value will produce JEDEC output..

Header Item Requirement: Optional


FUNCTION

This statement allow s the user to create personal keywords by encapsulating some logic as a function and giving it a name. This name can then be used in a logic equation to represent the function.

The syntax for user-defined functions is as follows:

FUNCTION name ([parameter0,...,parameter1])

{ body

}

Where,

name is any group of valid symbols used to reference the function. Do not use any of the CUPL reserved keywords.
parameter is an optional variable used to reference variables when the function is used in a logic equation. It cannot be an expression.
body is any combination of logic equations, truth tables, state-machine syntax, condition syntax, or user function.
( ) are parentheses used to enclose the parameter list.
{ } are braces used to enclose the body of the function.

Note:

Functions must be defined before they may be referenced. Functions are not recursive; that is, a function body may not include a reference  of the function being defined.

Example:

The following example shows how to define an exclusive OR function:

FUNCTION  xor(in1, in2) {

/* in1 and in2 are parameters */

xor = in1 $ in2 ;

}

This function after being defined can be used and equations where inputs A and B are passed as parameters and Y is the output.

Y = xor (A, B) ;

This is equivalent to:

Y = A $ B ;


FUSE

This statement allows the user to set the state of specific fuses in the JEDEC file to a blown, (1 state) or not blown (0) state. It is not recommended to use this statement for Atmel Devices.

Warning:

Do not use this statement to blow arbitary fuses!!
If you have any question regarding when to use this statement please contact Logical Devices or Atmel PLD Applications first.


IF

This state machine syntax describes the conditions when a transition will be made from the present to the next state.

See Also State-Machinefor more information.


location
LOCATION(LOC)

This is a field of the header section of the PLD source file.  It is for documentation only.  It is meant for storing the board location where the device will be inserted.

Header Item Requirement: Optional


MIN

This declaration statement overrides, for specified variables, the minimization level specified on the command line when running CUPL. This declaration permits specifying different level of logic minimization for different outputs in the same design.

The syntax for this statement is as follows:

MIN var [.ext] = level ;

Where,

var is a single variable declared in the file or a list of variables grouped using the list notation; that is, [var, var,...,var]
.ext is an optional extension that identifies the function of the variable.
level is an integer between 0 and 4, that defines the minimization level
; is a semicolon to mark the end of the statement

There are five minimizations levels to choose from. These are:

level = 0	No minimization
level = 1	Quick Minimization (Default setting)
level = 2	Quine McCluskey Minimization
level = 3	Presto Minimization
level = 4	Espresso Minimization

Example:

The following are examples using the MIN declaration.

MIN async_out = 0;  /* No reduction for this output */

MIN [outa,outb] = 2;  /* Use Quine McCluskey Minimization for these outputs */

MIN [count.d]    = 4; /* Use Expresso Minimization for this output */

Using the MIN declaration  ill apply the selected logic minimization strategy to only the outputs specified by the MIN statement. All other outputs in the source file will be minimized by one of the -m0 through -m4 option flags specified on the command line.


NAME

This PLD source file header item defines the filename for the PLD source file. The NAME field can accomodate files names up to 32 characters long. However, some operating systems such as DOS only allow 8 characters for the filename. The NAME specfied by this field also determines the name for the JEDEC download file.

Header Item Requirement: Required


NODE

This statement is used to declare variable name for buried logic functions in a CPLD device

Do not use this statement for Atmel CPLD devices.

See Also PINNODEfor more information

NOTE:

Do not use this statement to specify buried nodes for Atmel CPLD devices. Use the PINNODE statement instead


OUT

This state machine syntax specifies the logic values (High or Low) for non-registered (asynchronous) outpout associated with a given present state, and defines when that variable is logically asserted. The logical state of the output variable specified by this statement depends on the whether the variable is asserted active-HI or active-LO in the PLD source file.

See Also State-Machine  for more information


PARTNO

This PLD source file Header item, specifies the companys proprietary part number. For  Atmel ATF16v8/20v8/22v10 devices, the first eight characters are ASCII encoded to represent the devicess 64-bit Universal Electronic Signature (UES) data. If an Atmel  ATF16v8/20v8/22v10 device is used to replace a GAL-type device which has data in the field them this Header item is required.

Header Item Requirement: Optional


PIN

The PIN declaration statement declares the pin numbers used by a particular design and assigns them symbolic variable names. This statement can also be used to define the polarity (active-HI or active-LO) of the input or output signal declared by this statement.

The syntax for this statement follows:

PIN pin_n= [ ! ]var ;

Where,

PIN is a keyword to declare the pin numbers and assign them variable names
pin_n is a deciman pin number or a list of pin numbers grouped using the list notation; that is, [pin_n 1, pin_n 2 ... pin_n n]
! is an optional exclamation point to define the polarity of the input or output signal.
= is the assignment operator
var is a single variable name of a list of variables grouped using the list notation; that is [var, var ... var]
; is a semicolon to mark the end of the pin declaration statement.

Examples:

The following examples shows how to used the pin statement for both active-HI and active-LO pins:

Pin 2 = A ;  /* Define signal A to be placed on pin 2. A is active-HI */
Pin 3 = !B; /* Define signal B to be placed on pin3. B is active-LO

The polarity of the signal defines the logic state (1, 0) that the signal is asserted to when it is considered to be true. In the above example signal B will be asserted logic 0 (active-LO) when it is true. Signal A will be asserted logic 1 (active-HI) when it is true.

The signals defined with the PIN statement may be either inputs, outputs or bi-directional pins. The nature of the device pin is not specified in the PIN declaration. The compiler infers the nature of a pin from the way the pin variable name is used in the logic equations specified in the PLD source file. If the pin number specifed for a signal is incompatible with the physical characteristics of the target PLD device, CUPL will display an error message denoting improper usage of the pin.
If no target PLD is specified in the source file; For example, a Virtual Devicepin is declared as the Device declaration in the header section of the PLD source file, then pin numbers may be omitted.


PINNODE

This statement is used to define buried logic functions in an Atmel CPLD device by assigning a node number to a symbolic variable name. The polarity of the buried signal can be also be defined active-HI or active-LO with this statement.

The syntax of this statement is as follows:

PINNODE node_n = [ ! ]var ;

Where,

PINNODE is a keyword to declare the node numbers and assign them variable names
node_n is a decimal node number of a list of node numbers grouped using the list notation; that is, [node_n1,node_n2 ... node_nn]
! is an optional exclamation point to define the polarity of the internal signal
= is the assignment operator
var is a single variable name or list of variables grouped using the list notation; that is, [var,var ...var]
; is a semicolon used to mark the end of the statement.

Most internal nodes in Atmel devices except for foldback nodes on the ATF1500 family are active-HI; therefore, the exclamation point should not be used to define the polarity of an internal signal as active-LO. Refer to the internal node number listing given in the Atmel Datasheet or Databook for the target Atmel CPLD device you are designing with before assigning node numbers.You should also be aware of the architecture of the target Atmel CPLD device to determine the proper placement of node numbers. Assigning node numbers incorrectly will generate compiler errors or prevent the design from functioning properly. Some Atmel devices such as the ATF1500 family do not require node numbers to be assigned. Other Atmel devices (For example, the ATV750B/2500B) will require node numbers to be assigned for all buried logic functions used in the device.

Example:

The following are examples of the use of the PINNODE statement:

PINNODE [29..34] = [State0..5];  /* Define the node numbers for several buried signals */
PINNODE 25 = Buried;  /* Define the node number for a buried signal */

Note:

If buried logic functions are not assigned node numbers by using this statement,  certain Atmel CPLD devices (For example, ATF1500 family) will automatically assign node numbers when the design is fit into the Atmel device. Other Atmel CPLD devices, however, will require using this statement to assign node number for all buried logic functions.
Contact Atmel PLD Applications or Logical Devices if you need for more information about this statement.


PRESENT

This state machine syntax defines the present state that a state machine description has entered.

All condional transitions from this present state to the next state need to be defined within this statement

See Also State-Machine for more information


revision
REVISION(REV)

This PLD source file Header Item specifies the current revision of the design described in the source file

Header Item Requirement: Optional


SEQUENCE

This statement defines the beginning of a state machine description in the PLD source file. The SEQUENCE statement identifies the outputs of a state machine and is followed by statement that define the function of the state machine.  CUPL will implement the logic equations using the D-type register.

See Also State-Machine for more information


SEQUENCED

This statement is similar to the SEQUENCE statement except that it defines that the logic equations generated by the state machine description are implemented as D-type registers. CUPL will automatically generate the logic equations for the specified register type.

See Also State-Machine for more information


SEQUENCET

This statement is similar to the SEQUENCE statement except that the logic equations generated by the state machine description are implemented using T-type registers. CUPL will automatically generate the logic equations for the specified register type.

See Also State-Machine  for more information


SEQUENCEJK

This statement is similar to the SEQUENCE statement except that the logic equation generated by the state machine description are implemented using J-K-type registers. CUPL will automatically generate the logic equations for the specified register type.

See Also State-Machine for more information


SEQUENCERS

This statement is similar to the SEQUENCE statement except that the logic equation generated by the state machine descriptions are implemented using R-S-type registers. CUPL will automatically generate the logic equations for the specified register type.

See Also State-Machine for more information


TABLE

This statement allows a logic function to be defined in a tabular format. In some cases, this method may be more perferable than describing the logic function that in boolean equation form.

See Also Truth-Table for more information


PROPERTY

This statement allows additional design information (For example, fitter pin assignment strategies) associated with an external processing module such as, the Atmel device fitter  to be specified in the PLD source file.

Note:

The ATF1500 family of devices have several fitting strategies which can be specified in CUPL by using the PROPERTY statement. For a more detail listing of these strategies consult the fitter manual for the appropriate Atmel device or contact Atmel PLD Applications

The syntax for this statement for Atmel devices is as follows:

PROPERTY Atmel {option} ;

Where,

PROPERTY is a keyword used by CUPL to identify Atmel Specific Device or fitter information.
option represents Atmel fitter option normally specified on the command line. Examples of options are: Pin-Preassignment options (KEEP, TRY, IGNORE), Logic Optimization strategies and other device specific information.
{ } are braces used to enclose the option name
; is a semicolon used to denote the end of an expression

A separate PROPERTY statement is required for each device specific option. For a listing of available options to use with the property statement consult the fitter manual for the appropriate Atmel ATF1500 family device. The PROPERTY statement is not used with Atmel ATV750B and ATV2500B devices.

Example:

PROPERTY Atmel { preassign keep };  /* Fit design with original pin assignments only */
PROPERTY Atmel {foldback_logic = node};  /* Retain signal node as a foldback logic node */


DECLARE

The statement is similar to the PROPERTY statement where it allows you to specify device specific directives. However, it is NOT used for Atmel Devices

See Also  Property statement for more information

Note:

Do not use this statement for Atmel Devices use the PROPERTY statement instead


DEMORGAN

This statement is used to control the application of DeMorgans Theorem to a specific set of logic variables or to the entire PLD source file.

The syntax for this statement follows:

DEMORGAN [var_list] = Demorgan_Option ;

Where,

DEMORGAN is a keyword used to specify that De-morgan optimization is to be applied to selected variable(s) indicated in the variable list
var_list is a list of variables grouped using list notation. That is, [var,var, ...var]
Demorgan_Option is a number between 0 to 2 which represents the type of De-morganzation optimization performed on the variable(s) indicated in the variable list.
The option level are defined below:
0	Standard expression evaluation no optimization (Default value)
1	Force DeMorgan of expression for each variable in variable list
2	Apply DeMorgans theorem to each variable in the variable list to see if the number of product terms can be reduced.
; is a semicolon used to denote the end of the expression.

Alternately, by selecting the Optimization button in the Compile Menu in WINCUPL allows any of the DeMorgan options described above to be applied to the entire PLD source file.

Note:

The DeMorgan statement can only be used with devices that have programmable output polarity. For example, any device that has a polarity fuse and/or mux. Such as the ATF22V10B, ATV750/B, ATV2500/B. This statement can also be used for virtual device types.

Example:

Device	p22v10;

Pin 16 = !x;

DEMORGAN [x] = 2; /* Choose best usage of product terms */

x= a # b; /* Where a and b are inputs */

CUPL will generate a DeMorgan equivalent expression for the output as;

!x = !a & !b;

since this expression uses the least number of product terms.


REGISTER_SELECT

This statement allow the user to convert logic equations for a specific set of logic variable to different register types automatically. CUPL will generate equivalent logic expressions for the target register type

The syntax for this statement follows:

REGISTER_SELECT [var_list] = register_type ;

Where,

REGISTER_SELECT is a keyword  which allows the user to determine what register type to convert registered outputs defined the variable list.
var_list is a list of variable(s) grouped in list notation. That is, [var,var,,,,var]
register_type is a number between 0 and 5, that specifies the target register type to convert the logic equations. The option settings are described below:
0	use the specified register

1	D type Flip-Flop

2	T-type Flip-Flop

3	JK-type Flip-Flop

4	SR-type Flip-Flop

5	select best usage of product terms between D and T.
; is a semicolon used to denote the end of an expression.

Some  Atmel devices, such as the ATF1500 family while implementing D-type registers in the macrocells allow the design to be captured using T,J-K, or S-R flip-flop. The REGISTER_SELECT keyword permits the user to write logic equations using these flip-flop type and allow CUPL to automatically convert these logic equations into D-type registers which are supported in the architecture of the device. This keyword can also be used to convert D-type registers T-type flip-flops which are support on the Atmel ATV750B and ATV2500B devices. Converting counter functions in designs implemented with D-type register to T-type register can significantly reduce the number of product term used to implement these functions. If you want CUPL to decide if a specific logic equation in your design is best suited for D or T-type use option five (5) in the register type list.

Example:

The following example show how to convert logic originally defined using J-K registers to D-type registers.

REGISTER_SELECT [x] = 1;  /* Output variable x will be convert t0 a D-type register */
x.j = a;        /* Original Logic defined using J-K registers */
x.k = b;

When this expression is compiled by CUPL it will automatically generate the following D-type expression:

x.d => a & !x # a & !b #  !b & x;  /* Converted D-type expression */


ap
.AP

The .AP extension is used to set the Asynchonous Preset of a register to an expression. For example, the expression

Y.ap = A & B;

causes the register to be asynchronously preset when A and B are logically true. This feature is supported on the ATF1500 family of devices.


ar
.AR

The .AR extension is used to define the expression for Asynchronous Reset for a register. This is used in devices that have one or more product terms connected to the Asynchronous reset of the register. Devices which have a pin-controlled reset inputs, such as the Atmel ATF1500 family also use this suffix.


ck
.CK

The .CK extension is used to select a product term driven clock. Some devices have the capability to conect the clock for a register to one or more pins or to a product term. The .CK extension will select the product term. To connect the clock to a pin directly us the .CKMUXextension.

Other Atmel devices besides the ATV750B which have pin-controlled clock inputs also use this suffix.


ce
.CE

The .CE extension is used for D-type registers which have a clock enable input (D-CE registers) . It serves to specfiy the input to the Clock enable term of the register. In devices that have D-CE registers such as the ATV2500B and the ATF1500 family, the CE terms if not used must be set to a binary 1, so that these registers will behave as D registers. Normally, the CUPL compiler or Atmel Atf1500 family fitter will automatically do this for you.


ckmux
.CKMUX

The .CKMUX extension is used to connect the pin clock to the register. This extension is used on the Atmel ATV750B device. Using this extension can reduce the number of product needed to implement the design into the Atmel device, and can increase the AC timing performance of the design.Other Atmel Devices such as the ATV2500B and ATF1500 family also have dedicated clock pins, by they are not specified with the .CKMUX extension. They use the .CK extension instead.


d
.D

The .D extension is used the specify the D input to a D-type register. This options causes the compiler to configure the macrocells in the Atmel PLD device to D-type registers. For Atmel

SPLDs such as the ATF16V8B/20V8B/22V10B, ATV750 and ATV2500H/L the .D extension must be used for registered logic. If is not, CUPL will generate an error.


dfb
.DFB

The .DFB extension is used when the macrocell on an Atmel device is configured for a combinatorial output but the D register still remains connected to the output. This configuration is supported on the ATV750B and ATV2500B devices. The .DFB allows the registered representation of the combinatorial output to be fedback internally into the Atmel Device. This suffix is not currently supported for CUPL V4.7a and above. However, if you are interested in using this feature please contact Atmel PLD Applications.


tfb
.TFB

The .TFB extension is used when the macrocell on an Atmel device is configured for a combinatorial output but the T register still remains connected to the output. This configuration is supported on the ATV750B and ATV2500B devices. The .TFB allows the registered representation of the combinatorial output to be fedback internally into the Atmel Device. This suffix is not currently supported for CUPL V4.7a and above. However, if you are interested in using this feature please contact Atmel PLD Applications.


io
.IO

The .IO extension is used to select the pin feedback from the macrocell. This is useful, when a design requires using an I/O pin an input and also requires buried logic to be used within the same macrocell. It is also useful for implementing bi-directional outputs in CUPL. For examples on how implement bi-directional I/O in CUPL refer to the Tips for Using Test Vectors Application Note in the Atmel Configurable Logic databook, or contact Atmel PLD applications.


iol
.IOL

The .IOL extension is used to select feedback from a buried latch that is connected to an output macrocell by the pin feedback path. This feature is useful if you want to pre-latch an input before it is fed internally into the device. This feature is supported on the ATF1500 family of devices with 128 macrocells or greater.


jk
.JK

The .J and .K externsions are used to specify the J and K inputs to a J-K register. Logic equations using these externsions can written and the REGISTER_SELECTkeyword when the D or T-type target register is specified. This keyword is supported in CUPL versions 4.6 and greater.


sr
.SR

The .R and .S extensions are used to specify the R (reset)  and S (set) inputs to a SR register. Logic equations for the ATF1500 family can be written using these extensions if the REGISTER_SELECTkeyword is used and a D or T-type target register is specified. This keyword is supported in CUPL versions 4.6 and greater.


l
.L

The .L extension is used to specify an input to a latch. This extension is required to use the level-triggered latch feature available on the ATF1500 family of devices. The use of the .L extension causes the compiler to configure the macrocell as a latched output.


le
.LE

The .LE extension is used to specify the latch enable equation for a latch. It is required for designs using the level-triggered latch feature available on the ATF1500 family of devices. The .LE extension causes a product term to be connected to the latch enable.


oe
.OE

The .OE extension is used to specify a product term driven output enable signal. It is required for using bi-directional I/O and the individually programmable output-enable product terms available on Atmel ATV750/B and ATV2500/B and ATF1500 family of devices. Atmel Devices which have a pin-controlled OE inputs, such as the ATF1500 family also use this suffix.


sp
.SP

The .SP extension is used to set the Synchonous Preset of a register to an expression. For example, the equation:

Y.SP = A & B ; /* A and B are inputs */

causes the output Y to be preset synchronous with the local clock used in the macrocell when inputs A and B are true. This feature is supported on Atmel ATF22V10B, ATV750/B and ATV2500/B devices which share Synchronous preset product terms.


t
.T

The .T extension specifies the T input for a T-type register. The use of the T extension causes the compiler to configure the macrocell in the Atmel CPLD devices as T-type registers. This feature is supported on the Atmel ATV750B/2500B and ATF1500 family of devices.


int
.INT

The .INT extension is used for selecting an internal feedback path. This could be used to specify the buried combinatorial feedback path for either a registered or combinatorial output. This feature is available for the ATF1500 family of devices with 128 or greater macrocells. This feature is not currently supported on WINCUPL V4.7a. If you are interested in using this feature contact Atmel PLD applications.


dq
.DQ

The .DQ extension is used to specify an input D register. use of the .DQ externsion actually configures the input as registered. The .DQ extension is not used to specify the Q output from an output D type register. This feature is available on the ATF1500 family of device with 128 or greater macrocell. This feature is not currently support on WINCUPL V4.7b. If you are interested in using this feature please contact Atmel PLD Applications.


lq
.LQ

The .LQ extension is used to specify an input latch. Use of the .LQ extension actually configures the input as latched. The .LQ extension is not used to specify the Q output from an output latch.

This feature is available on the ATF1500 family of devices with 128 or more macrocells. It is not currently supported by WINCUPL V4.7b. If you are interested in using this feature contact Atmel PLD applications.