Prelab 2: Make a 1-bit Adder

Lab 2 will guide you through building and testing an ALU in Xilinx. This prelab gets you ready by having you build the first piece: a 1-bit adder. You should perform this prelab individually.

Goals:

  1. Create a new project in Xilinx
  2. Create a 1-bit adder in schematic form
  3. Test your 1-bit adder for proper operation

Make sure your name is on all the files you create or edit for this prelab.

Building a 1-bit Adder

  1. Pull changes from your GIT repository.

    • Open your repository in File Explorer
    • Right-click on it and select "Git Bash Here"
    • Pull changes from the server using git pull. There should be a lab02 directory. You will save your work for the prelab in there.

  2. Start ISE Design Suite 14.7 (Xilinx). This is probably on your desktop and looks like a green chevron. You used this in the previous lab.

    • It may be on your desktop.

    If you can't find it on the desktop, try:

    • Start → All Programs → Xilinx Design Tools → ISE Design Suite 14.7 → ISE Design Tools → 64-bit Project Navigator
    • Search for "ISE Design Suite" in the windows menu.

  3. Create a new project:

    • Select "File" → "New Project..." to open the "New Project Wizard."

    • In the "Create New Project" dialog:

      • enter "alu" for the "Name"
      • choose the "Location" where you want the project (create it in your GIT repository in the lab02 directory)
      • Important: add /work to the end of the "Working Directory" field
      • select "Schematic" as the "Top-Level Source Type"

      and click "Next"

    • In the "Project Settings" dialog, enter the following properties:

      • Family: Spartan3E
      • Device: XC3S500E
      • Package: FG320
      • Speed: -4
      • Synthesis Tool: XST (VHDL/Verilog)
      • Simulator: ISim (VHDL/Verilog)
      • Prefered Language: Verilog

      and click "Next".

    • Click "Finish" in the "Project Summary" dialog.

    Note: You can change the project properties by right clicking on the device (i.e. xc3s500e-4fg320) in the "Hierarchy" section of the "Design" tab and selecting "Design Properties..."

  4. Add a new source to the project. There are a number of ways that you can do this, choose one:

    • Right click on the device in the "Hierarchy" section of the "Design" tab and select "New Source..."
    • Select "Project"→"New Source..."
    • Click the "New Source" icon in the toolbar.

    Using any of these options, the "New Source Wizard" should appear.

    1. In the "Select Source Type" dialog, select "Schematic", enter "add1b" as the "File name:" and click "Next".
    2. In the "Summary" dialog, click "Finish".

  5. In add1b.sch implement the following logic:

    r = (ci & ~a & ~b) | (~ci & a & ~b) | (~ci & ~a & b) | (ci & a & b)

    and

    co = (ci & a) | (ci & b) | (a & b)

    where a and b are inputs to the adder, ci is the carry-in, r is the result, and co is the carry-out.

    • You should build the logic using and gates, or gates and inverters, which are all available in the "Symbols" tab.

    • To search for a symbol, type the first part of a symbols name in the "Symbol Name Filter".

    • To add a symbol to your schematic, select a symbol in the symbol pane (this will switch to "add symbol" mode) and click in the schematic. Clicking again will place another symbol. Pushing "Esc" or right-clicking will cancel "add symbol" mode.

    • To connect the symbols click the "Add Wire" icon (a blue pencil drawing a red wire) in the vertical toolbar. Click and drag in the schematic to specify a wire between a single pair of points. Use clicks (no drag) to specify a sequence of connected wire points. Double click will terminate the sequence.

    • To add input and output pins click the "Add I/O Marker" icon (a gate going right and a gate going left) in the vertical toolbar.

    • To name the input and output pins, click the "Add Net Name" icon (abc over a blue wire) in the toolbar and fill in "Name" in the "Options" pane.

    • To check your schematic click "Check Schematic" from the toolbar.

    Try to create your own design. However, if you get stuck, you can take a look at this example.

  6. In the "Design" tab "Implemenetation" view, make sure add1b.sch is selected and set as the top level module (a little green square over two gray squares). Right click and set it if necessary. Then, in the lower half of the panel, double click "Synthesize". Correct any errors.

  7. Create a testbench.

    1. At the top of the "Design" tab, select the "Simulation" view.
    2. Add a new source to the project.
      • For source type select "Verilog Test Fixture" and filename add1b_tb_0.
      • On the "Associate Source" dialog select "add1b" and click "Next".
      • Click "Finish".
    3. In the "Hierarchy" section of the "Design" tab, double-click on add1btb0.v and examine the test bench.

    4. Edit the verilog code to fully test the adder.

      • Feel free to change the module name to something more reasonable. I used add1b_tb_0.

      • Delete the following section:

        'ifdef auto_init
 initial begin
 ci = 0;
 b = 0;
 a = 0;
'endif

      • Add the following section in its place:

        initial begin
  ci = 0;
  b = 0;
  a = 0;
  // Wait 100ns for the simulator to finish initializing
  #100;
  a = 1;
  #1;
  if ((r == 1) && (co == 0))
    $display("okay 1");
  else
    $display("fail 1");
end

        Notes on the verilog code:

        • You don't have to worry about fully understanding all of the code right now.
        • "ci = 0" initializes the signal ci to 0.
          Constants are assumed to be decimal integers unless specified otherwise. For example "4'b0101" specifies a 4-bit binary value and "4'h5" specifies the same thing as a 4-bit hexidecimal value.
        • "#100" causes a delay if 100 time units.
        • "$display" will print a message on the simulation console.

      • Add additional verilog code inside the initial block to fully test the adder. Consider copying and pasting some code. You should have several good tests for each operation.

  8. Perform a behavioral simulation of your design using Xilinx's ISim tool:

    1. At the top of the "Design" tab, select the "Simulation" view.
    2. Make sure that the drop-down right under the view selector is set to "Behavioral".
    3. In the "Hierarchy" section of the "Design" tab, select the testbench you wish to run (probably add1b_tb_0)
    4. In the "Processes" section of the "Design" tab, expand the "ISim Simulator" entry, and double-click the "Simulate Behavioral Model" entry.
    5. In the ISim window select View > Zoom > To Full View to show the entire waveform. You should see green signals related to your design. If you see red or blue signals after the 100ns mark, something is wrong in your testbench or design; close ISim and correct the errors.
    6. Verify correct results. Press the 'Play hourglass' symbol in the simulator to step forward. Make sure the waveform is correct. Modify your design if necessary.
    7. Close ISim.

  9. Create a schematic symbol for add1b.sch.

    • At the top of the "Design" tab, select the "Implementation" view. Select the schematic you wish to build.
    • In the "Processes" section of the "Design" tab, expand the "Design Utilities" entry, and double-click the "Create Schematics Symbol" entry.

Finishing the prelab

  1. Commit your project to GIT by following these steps:
    • Make sure your name is in any code files you created.
    • Clean up your project (Select "Cleanup Project Files..." from the "Project" menu)
    • Remove the work directory (inside your project directory)
    • Put your ALU project onto the GIT server:
      • Add your ALU project files to GIT (git add alu/)
      • Commit your changes to GIT (git commit -m "finished the prelab")
      • Push your changes to the server (git push)

In lab, you will use the code you created here to create an ALU. You will be assigned a lab partner in lab, so be ready to explain how your adder works.