module reg16bitWriteEnable(DataOut, DataIn, WriteEnable, Reset, Clock);
	input [15:0]  DataIn;
	input Clock, Reset, WriteEnable;

	output [15:0] DataOut;

	reg [15:0] DataOut;

	always @ (posedge Clock or posedge Reset )
        begin
	 if( Reset )
		DataOut <=  0;	//Clear the register when Reset = 1
	 else
	    if ( WriteEnable )
		DataOut <=  DataIn;
         end

endmodule

module reg16bit(DataOut, DataIn, Reset, Clock);
	input [15:0]  DataIn;
	input Clock, Reset;

	output [15:0] DataOut;

	reg [15:0] DataOut;

	always @ (posedge Clock or posedge Reset )
        begin
	 if( Reset )
		DataOut <=  0;	//Clear the register when Reset = 1
	 else
		DataOut <=  DataIn;
         end

endmodule