Syllabus[1]

Week starting

Day

Topics

Reading

(Sections)

Due

08/29

R[2]/F[3]

Course overview/Project Overview

09/05

M/T

Intro. To MIPS, SPIM

2.3,2.5

T/W

Conditional statements

2.6

Teams, Proposed meeting times[4]

R/F

Procedures

2.7

09/12

M/T

Addressing modes

2.9

T/W

Representing instructions

2.4

R/F

Exceptions

09/19

M/T

Computer arithmetic/Xilinx installation

3.3

T/W

Xilinx exercise

Assembly Language and Machine Language specifications (M1)

R/F

Group Meetings and Project Time

09/26

M/T

Register Transfer Language

5.5

T/W

Exceptions/ Xilinx exercise

R/F

Exam 1

10/03

M/T

Single cycle datapath implementation

5.3-4

RTL Specifications (M2)

T/W

Multi-cycle datapath implementation

5.5

R/F

ALU Design/ Xilinx Exercise

3.3

10/10

M/T

Xilinx Exercise

T/W

Group Meetings and Project Time

Datapath Design and Component Specification. (M3)

Fall break

10/17

M/T

Control design (FSM)/ Xilinx Exercise

5.5

T/W

Control design (Micro-programming)/Xilinx Exercise

5.53-54

Datapath Design and Component Specification. (M3)

R/F

Group Meetings and Project Time

10/24

M/T

Xilinx Exercise

T/W

Performance

Ch. 4

Control unit design and components implementation (M4)

R/F

Group meetings and project time

10/31

M/T

 Floating Point

3.30-31,48

T/W

Group meetings and project time

2.7

Component Integration and Datapath Testing (M5)

R/F

Exam 2

11/07

M/T

Recursion and stacks

T/W

Group meetings and project time

Final Xilinx model

R/F

Group meetings and project time

Final project report

11/14

Finals week (Project presentations)