StateCAD ver 0 0 0 0 0 0 0 0 0 0 1281 0 0 0 Copyright 1992-2001 Xilinx, Inc.All rights reserved.
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header title 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
header clock 0 0 0 0 0 0 0 0 0 0 5 7 1 0 CLK
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fitter on 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
check for 0 0 0 0 0 0 0 0 0 0 142 0 0 0 
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 ALU1
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALU1
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 ALU2
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALU2
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 ALUControl
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 ALUControl
variable add 0 0 0 0 0 0 0 0 0 0 8 7 1 0 ASelect
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 ASelect
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 ASelect0
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 ASelect0
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 ASelect1
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 ASelect1
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 BitFifteen
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BitFifteen
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 BitFunction
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 BitFunction
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 BitResult
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BitResult
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 Bs1
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bs1
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 Bs2
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bs2
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 BTJ2
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTJ2
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 BTL1
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTL1
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 BTL2
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTL2
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 Copy1
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Copy1
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 Cycle1
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Cycle1
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 Cycle2
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Cycle2
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 EPCWrite
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 EPCWrite
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 Exception
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Exception
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 Exception2
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Exception2
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 ExceptionReset
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 ExceptionReset
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 GlobalReset
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 GlobalReset
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 InitPC
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 InitPC
variable add 0 0 0 0 0 0 0 0 0 0 8 7 1 0 Input1Select
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 Input1Select
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 Input1Select0
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 Input1Select0
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 Input1Select1
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 Input1Select1
variable add 0 0 0 0 0 0 0 0 0 0 8 7 1 0 Input2Select
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 Input2Select
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 Input2Select0
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 Input2Select0
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 Input2Select1
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 Input2Select1
variable add 0 0 0 0 0 0 0 0 0 0 2 7 3 0 IntClear
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 IntClear
variable add 0 0 0 0 0 0 0 0 0 0 8 7 1 0 InterruptWait
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 InterruptWait
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 InterruptWait0
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 InterruptWait0
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 InterruptWait1
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 InterruptWait1
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 InterruptWait2
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 InterruptWait2
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 InterruptWait3
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 InterruptWait3
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 InterruptWait4
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 InterruptWait4
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 InterruptWait5
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 InterruptWait5
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 InterruptWait6
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 InterruptWait6
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 InterruptWait7
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 InterruptWait7
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 InterruptWait8
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 InterruptWait8
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 InterruptWait9
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 InterruptWait9
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 InterruptWait10
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 InterruptWait10
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 InterruptWait11
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 InterruptWait11
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 InterruptWait12
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 InterruptWait12
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 InterruptWait13
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 InterruptWait13
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 InterruptWait14
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 InterruptWait14
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 InterruptWait15
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 InterruptWait15
variable add 0 0 0 0 0 0 0 0 0 0 8 7 1 0 IR
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 IR
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 IR0
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IR0
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 IR1
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IR1
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 IR2
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IR2
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 IR3
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IR3
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 IR4
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IR4
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 IR5
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IR5
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 IR6
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IR6
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 IR7
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IR7
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 IR8
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IR8
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 IR9
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IR9
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 IR10
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IR10
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 IR11
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IR11
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 IR12
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IR12
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 IR13
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IR13
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 IR14
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IR14
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 IR15
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IR15
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 IRWrite
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 IRWrite
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 Latch1
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Latch1
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 LatchOut
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 LatchOut
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 Li1
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Li1
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 Li2
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Li2
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 LiNEWneeded
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LiNEWneeded
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 LW2
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LW2
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 LWMemory1
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LWMemory1
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 LWReg1
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LWReg1
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 MemAddrSelect
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 MemAddrSelect
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 MemWrite
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 MemWrite
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 Needed2scomp
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Needed2scomp
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 Not12scomp
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Not12scomp
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 Not22scomp
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Not22scomp
variable add 0 0 0 0 0 0 0 0 0 0 8 7 1 0 PCSelect
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 PCSelect
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 PCSelect0
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 PCSelect0
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 PCSelect1
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 PCSelect1
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 PCWrite
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 PCWrite
variable add 0 0 0 0 0 0 0 0 0 0 8 7 1 0 Read1Select
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 Read1Select
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 Read1Select0
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 Read1Select0
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 Read1Select1
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 Read1Select1
variable add 0 0 0 0 0 0 0 0 0 0 8 7 1 0 Read2Select
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 Read2Select
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 Read2Select0
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 Read2Select0
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 Read2Select1
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 Read2Select1
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 ReadPrefix
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 ReadPrefix
variable add 0 0 0 0 0 0 0 0 0 0 8 7 1 0 RegDataSelect
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 RegDataSelect
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 RegDataSelect0
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 RegDataSelect0
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 RegDataSelect1
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 RegDataSelect1
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 RegDataSelect2
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 RegDataSelect2
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 RegDataSelect3
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 RegDataSelect3
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 RegWrite
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 RegWrite
variable add 0 0 0 0 0 0 0 0 0 0 8 7 1 0 RegWriteSelect
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 RegWriteSelect
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 RegWriteSelect0
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 RegWriteSelect0
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 RegWriteSelect1
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 RegWriteSelect1
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 RegWriteSelect2
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 RegWriteSelect2
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 RES5
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RES5
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 RES6
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RES6
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 RES7
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RES7
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 RES8
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RES8
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 RES9
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RES9
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 RES10
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RES10
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 RES11
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RES11
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 RES12
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RES12
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 RES13
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RES13
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 RES14
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RES14
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 RES15
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RES15
variable add 0 0 0 0 0 0 0 0 0 0 1 7 1 0 RESET
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESET
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 ResetState
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ResetState
variable add 0 0 0 0 0 0 0 0 0 0 2 7 1 0 ResSelect
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 ResSelect
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 Rfi1
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rfi1
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 Rfi2
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rfi2
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 Sex1
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Sex1
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 Shift1
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Shift1
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 Shift2
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Shift2
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 SW1
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW1
variable add 0 0 0 0 0 0 0 0 0 0 4 7 0 0 SW2
variable oe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW2
variable add 0 0 0 0 0 0 0 0 0 0 2 7 3 0 SyscondWrite
variable oe 0 0 0 0 0 0 0 0 0 0 16 0 0 0 SyscondWrite
state add 900 -2300 1358 -3441 900 -3441 1358 -3441 13 1 0 224 0 0 ALU1PCWrite = '0';
EPCWrite = '0';
IRWrite = '0';
MemWrite = '0';
Input2Select = ^b00;
Input1Select = ^b01;
ResSelect = '0';
RegWrite = '0';
ALUControl = '1';
SyscondWrite = '1';
state add 200 -3150 658 -4289 200 -4289 658 -4289 13 2 0 224 0 0 ALU2PCWrite = '0';
EPCWrite = '0';
IRWrite = '0';
MemWrite = '0';
ResSelect = '0';
RegWrite = '1';
RegDataSelect = ^b010;
RegWriteSelect = ^b010;
Read2Select = ^b10;
Read1Select = ^b10;
state add 5400 -2250 5858 -3022 5400 -3022 5858 -3022 13 3 0 224 0 0 Bs1PCWrite = '0';
EPCWrite = '0';
BitFunction = '1';
IRWrite = '0';
MemWrite = '0';
ASelect = ^b11;
RegWrite = '0';
ExceptionReset = '0';
state add 6900 -2950 7358 -4161 6900 -4161 7358 -4161 13 4 0 224 0 0 Bs2PCWrite = '0';
EPCWrite = '0';
IRWrite = '0';
MemWrite = '0';
RegWrite = '1';
RegDataSelect = ^b001;
RegWriteSelect = ^b010;
Read2Select = ^b10;
Read1Select = ^b10;
ExceptionReset = '0';
state add 2950 -3600 3400 -4350 2950 -4350 3400 -4500 13 5 0 224 0 0 BTJ2PCSelect = ^b10;
PCWrite = '1';
EPCWrite = '0';
IRWrite = '0';
MemWrite = '0';
Read2Select = ^b10;
Read1Select = ^b10;
state add 3200 -2700 3658 -3398 3200 -3398 3658 -3398 13 6 0 224 0 0 BTL1PCWrite = '0';
EPCWrite = '0';
BitFunction = '0';
IRWrite = '0';
MemWrite = '0';
RegWrite = '0';
Read2Select = ^b01;
state add 3550 -3500 4008 -4788 3550 -4788 4008 -4788 13 7 0 224 0 0 BTL2PCSelect = ^b10;
PCWrite = '1';
EPCWrite = '0';
IRWrite = '0';
MemWrite = '0';
RegWrite = '1';
RegDataSelect = ^b111;
RegWriteSelect = ^b100;
Read2Select = ^b10;
Read1Select = ^b10;
state add 6750 -1350 7208 -2489 6750 -2489 7208 -2489 13 8 0 224 0 0 Copy1PCWrite = '0';
EPCWrite = '0';
IRWrite = '0';
MemWrite = '0';
ReadPrefix = '0';
RegWrite = '1';
RegDataSelect = ^b000;
RegWriteSelect = ^b001;
Read2Select = ^b10;
Read1Select = ^b10;
state add 950 -450 1504 -1951 950 -1951 1504 -1951 13 9 0 224 0 0 Cycle1MemAddrSelect = '0';
PCSelect = ^b00;
PCWrite = '1';
EPCWrite = '1';
IRWrite = '1';
MemWrite = '0';
Input1Select = ^b00;
Input2Select = ^b01;
ALUControl = '0';
RegWrite = '1';
RegDataSelect = ^b1000;
RegWriteSelect = ^b101;
GlobalReset = '0';
state add 1850 -700 2308 -1913 1850 -1913 2308 -1913 13 10 0 224 0 0 Cycle2PCWrite = '0';
EPCWrite = '0';
IRWrite = '0';
MemWrite = '0';
Input2Select = ^b10;
Input1Select = ^b11;
ResSelect = '0';
RegWrite = '0';
Read2Select = ^b00;
Read1Select = ^b01;
ASelect = ^b10;
state add 2100 -4227 2600 -7720 2100 -7720 2600 -7720 13 11 0 224 0 0 ExceptionPCSelect = ^b10;
PCWrite = BitFifteen AND (InterruptWait15 = '1' OR InterruptWait14 = '1' OR InterruptWait13 = '1' OR InterruptWait12 = '1' OR InterruptWait11 = '1' OR InterruptWait10 = '1' OR InterruptWait9 = '1' OR InterruptWait8 = '1' OR InterruptWait7 = '1' OR InterruptWait6 = '1' OR InterruptWait5 = '1' OR InterruptWait4 = '1' OR InterruptWait3 = '1' OR InterruptWait2 = '1' OR InterruptWait1 = '1' OR InterruptWait0 = '1');
EPCWrite = '0';
IRWrite = '0';
MemWrite = '0';
RegWriteSelect = ^b110;
RegWrite = InterruptWait14;
Read1Select = ^b10;
RegDataSelect = ^b1001;
state add 1200 -7314 1658 -7864 1200 -7864 1658 -7864 13 12 0 224 0 0 Exception2RegWriteSelect = ^b111;
RegDataSelect = ^b1010;
IntClear = '1';
RegWrite = '1';
state add 6300 -4250 6758 -5340 6300 -5340 6758 -5340 13 13 0 224 0 0 Latch1PCWrite = '0';
EPCWrite = '0';
IRWrite = '0';
MemWrite = '0';
RegWrite = '0';
Read1Select = ^b11;
Read2Select = ^b11;
LatchOut = '1';
state add 4800 -2500 5258 -3566 4800 -3566 5258 -3566 13 14 0 224 0 0 Li1PCWrite = '0';
EPCWrite = '0';
IRWrite = '0';
MemWrite = '0';
RegWrite = '1';
RegDataSelect = ^b011;
RegWriteSelect = ^b010;
Read2Select = ^b10;
Read1Select = ^b10;
state add 2100 -2750 2558 -3816 2100 -3816 2558 -3816 13 15 0 224 0 0 Li2PCWrite = '0';
EPCWrite = '0';
IRWrite = '0';
MemWrite = '0';
RegWrite = '1';
RegDataSelect = ^b101;
RegWriteSelect = ^b010;
Read2Select = ^b10;
Read1Select = ^b10;
state add 2050 -2450 2508 -2705 2050 -2705 2508 -2705 13 16 0 224 0 0 LiNEWneededRead2Select = ^b01;
state add 3694 -206 4307 -845 3694 -845 4307 -845 13 17 0 224 0 0 LW2ReadPrefix = '0';
ASelect = ^b00;
RegWrite = '1';
RegDataSelect=^b001;
RegWriteSelect=^b001;
Read2Select = ^b10;
Read1Select = ^b10;
state add 3000 -50 3450 -750 3000 -750 3450 -750 13 18 0 224 0 0 LWMemory1PCWrite = '0';
EPCWrite = '0';
IRWrite = '0';
MemWrite = '0';
ASelect = ^b00;
RegWrite = '0';
MemAddrSelect = '1';
state add 3200 -800 3658 -1645 3200 -1645 3658 -1645 13 19 0 224 0 0 LWReg1PCWrite = '0';
EPCWrite = '0';
IRWrite = '0';
MemWrite = '0';
ReadPrefix = '1';
ASelect = ^b10;
ResSelect = '0';
RegWrite = '0';
Read1Select = ^b00;
state add 7250 -2650 7708 -3054 7250 -3054 7708 -3054 13 20 0 224 0 0 Needed2scompInput1Select = ^b10;
Input2Select = ^b11;
state add 6000 -2000 6458 -2845 6000 -2845 6458 -2845 13 21 0 224 0 0 Not12scompPCWrite = '0';
EPCWrite = '0';
IRWrite = '0';
MemWrite = '0';
Input1Select = ^b01;
ASelect = ^b10;
ResSelect = '0';
ALUControl = '1';
state add 8200 -2500 8658 -3566 8200 -3566 8658 -3566 13 22 0 224 0 0 Not22scompPCWrite = '0';
EPCWrite = '0';
IRWrite = '0';
MemWrite = '0';
RegWrite = '1';
RegDataSelect = ^b010;
RegWriteSelect = ^b010;
Read2Select = ^b10;
Read1Select = ^b10;
state add 200 -255 818 -2045 200 -2045 818 -2045 13 23 0 224 0 0 ResetStateMemAddrSelect='0';
PCSelect=^b00;
PCWrite='1';
EPCWrite='0';
BitFunction='0';
IRWrite='0';
MemWrite='0';
ReadPrefix='0';
Input2Select=^b00;
Input1Select=^b00;
ASelect=^b00;
ResSelect='0';
RegWrite='0';
RegDataSelect=^b0000;
RegWriteSelect=^b000;
Read2Select=^b00;
Read1Select=^b00;
ALUControl='0';
ExceptionReset='0';
LatchOut='0';
GlobalReset='1';
InitPC = '1';
state add 5450 -3450 5908 -4223 5450 -4223 5908 -4223 13 24 0 224 0 0 Rfi1PCSelect = ^b01;
PCWrite = '1';
EPCWrite = '0';
IRWrite = '0';
MemWrite = '0';
ASelect = ^b10;
RegWrite = '0';
Read1Select = ^b10;
state add 7300 -3750 7758 -5258 7300 -5258 7758 -5258 13 25 0 224 0 0 Rfi2PCWrite = '0';
EPCWrite = '0';
BitFunction = '1';
IRWrite = '0';
MemWrite = '0';
ASelect = ^b11;
RegWrite = '1';
RegDataSelect = ^b001;
RegWriteSelect = ^b011;
Read2Select = ^b10;
Read1Select = ^b10;
ExceptionReset = '1';
state add 7600 -1050 8058 -2263 7600 -2263 8058 -2263 13 26 0 224 0 0 Sex1PCWrite = '0';
EPCWrite = '0';
IRWrite = '0';
MemWrite = '0';
ReadPrefix = '0';
ASelect = ^b00;
RegWrite = '1';
RegDataSelect = ^b100;
RegWriteSelect = ^b001;
Read2Select = ^b10;
Read1Select = ^b10;
state add 1450 -2800 1908 -3351 1450 -3351 1908 -3351 13 27 0 224 0 0 Shift1PCWrite = '0';
EPCWrite = '0';
IRWrite = '0';
MemWrite = '0';
ResSelect = '1';
RegWrite = '0';
state add 1000 -3850 1458 -4989 1000 -4989 1458 -4989 13 28 0 224 0 0 Shift2PCWrite = '0';
EPCWrite = '0';
IRWrite = '0';
MemWrite = '0';
ResSelect = '0';
RegWrite = '1';
RegDataSelect = ^b010;
RegWriteSelect = ^b010;
Read2Select = ^b10;
Read1Select = ^b10;
state add 5900 -50 6358 -969 5900 -969 6358 -969 13 29 0 224 0 0 SW1MemAddrSelect = '1';
PCWrite = '0';
EPCWrite = '0';
IRWrite = '0';
MemWrite = '1';
RegWrite = '0';
Read2Select = ^b10;
Read1Select = ^b10;
state add 6700 -150 7158 -1289 6700 -1289 7158 -1289 13 30 0 224 0 0 SW2PCWrite = '0';
EPCWrite = '0';
IRWrite = '0';
MemWrite = '0';
ReadPrefix = '1';
RegWrite = '1';
RegDataSelect = ^b001;
RegWriteSelect = ^b000;
Read2Select = ^b10;
Read1Select = ^b10;
state add 249 -89 274 -117 249 -117 274 -117 14 31 0 0 0 0 @default transition
state select 0 0 0 0 0 0 0 0 0 1 0 0 0 0 
state attribute 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sreg
state select 0 0 0 0 0 0 0 0 0 1 0 0 0 0 
transition add 0 0 0 0 0 0 0 0 0 2 0 0 0 0 
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graphic add 816 -3181 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 719 -3297 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 622 -3414 0 0 0 0 0 0 0 0 0 0 0 0 
state select 0 0 0 0 0 0 0 0 0 2 0 0 0 0 
transition add 0 0 0 0 0 0 0 0 0 11 0 0 0 0 
graphic add 472 -4278 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 1017 -4692 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 1562 -5106 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 2108 -5521 0 0 0 0 0 0 0 0 0 0 0 0 
state select 0 0 0 0 0 0 0 0 0 3 0 0 0 0 
transition add 0 0 0 0 0 0 0 0 0 4 0 0 0 0 
graphic add 5839 -2788 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 6200 -2956 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 6561 -3124 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 6922 -3292 0 0 0 0 0 0 0 0 0 0 0 0 
state select 0 0 0 0 0 0 0 0 0 4 0 0 0 0 
transition add 0 0 0 0 0 0 0 0 0 11 0 0 0 0 
graphic add 6931 -3864 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 5464 -4158 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 3996 -4453 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 2528 -4748 0 0 0 0 0 0 0 0 0 0 0 0 
state select 0 0 0 0 0 0 0 0 0 5 0 0 0 0 
transition add 0 0 0 0 0 0 0 0 0 11 0 0 0 0 
graphic add 3130 -4491 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 2910 -4474 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 2690 -4458 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 2470 -4442 0 0 0 0 0 0 0 0 0 0 0 0 
state select 0 0 0 0 0 0 0 0 0 6 0 0 0 0 
transition add 3250 -3498 3708 -3630 3250 -3630 3708 -3644 0 11 0 0 0 0 BitResult = '0' AND (IR11 = '0' OR IR11 = '1')
graphic add 3409 -3396 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 3122 -3891 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 2834 -4386 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 2545 -4884 0 0 0 0 0 0 0 0 0 0 0 0 
transition add 3450 -3298 3908 -3430 3450 -3430 3908 -3444 0 7 0 0 0 0 IR11 = '0' AND BitResult = '1'
graphic add 3560 -3334 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 3596 -3413 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 3633 -3494 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 3670 -3576 0 0 0 0 0 0 0 0 0 0 0 0 
transition add 2950 -3347 3408 -3479 2950 -3479 3408 -3493 0 5 0 0 0 0 IR11 = '1' AND BitResult = '1'
graphic add 3300 -3338 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 3276 -3428 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 3252 -3518 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 3227 -3612 0 0 0 0 0 0 0 0 0 0 0 0 
state select 0 0 0 0 0 0 0 0 0 7 0 0 0 0 
transition add 0 0 0 0 0 0 0 0 0 11 0 0 0 0 
graphic add 3706 -4754 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 3324 -4845 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 2942 -4936 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 2560 -5028 0 0 0 0 0 0 0 0 0 0 0 0 
state select 0 0 0 0 0 0 0 0 0 8 0 0 0 0 
transition add 0 0 0 0 0 0 0 0 0 11 0 0 0 0 
graphic add 6803 -2286 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 5370 -3056 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 3937 -3826 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 2504 -4597 0 0 0 0 0 0 0 0 0 0 0 0 
state select 0 0 0 0 0 0 0 0 0 9 0 0 0 0 
transition add 0 0 0 0 0 0 0 0 0 10 0 0 0 0 
graphic add 1503 -1216 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 1618 -1249 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 1734 -1283 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 1850 -1318 0 0 0 0 0 0 0 0 0 0 0 0 
state select 0 0 0 0 0 0 0 0 0 10 0 0 0 0 
transition add 5350 -642 5808 -1242 5350 -1242 5808 -1256 0 30 0 0 0 0 IR15 = '0' AND IR14 = '1' AND IR13 = '0' AND IR12 = '1' AND IR11 = '1'  AND RES15 = '0' AND RES14 = '0' AND RES13 = '0' AND RES12 = '0' AND RES11 = '0' AND RES10 = '0' AND RES9 = '0' AND RES8 = '0' AND RES7 = '0' AND RES6 = '0' AND RES5 = '0'
graphic add 2302 -1169 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 3769 -1057 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 5236 -945 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 6704 -834 0 0 0 0 0 0 0 0 0 0 0 0 
transition add 2147 -2236 2605 -2472 2147 -2472 2605 -2486 0 16 0 0 0 0 IR15 = '0' AND IR14 = '1' AND IR13 = '0' AND IR12 = '0' AND IR11 = '1' AND IR0='0'
graphic add 2133 -1895 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 2152 -2083 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 2171 -2271 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 2190 -2459 0 0 0 0 0 0 0 0 0 0 0 0 
transition add 5625 -4303 6083 -4527 5625 -4527 6083 -4541 0 13 0 0 0 0 IR15 = '0' AND IR14 = '1' AND IR13 = '1' AND IR12 = '1' AND IR11 = '0'
graphic add 2273 -1626 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 3615 -2668 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 4957 -3710 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 6300 -4753 0 0 0 0 0 0 0 0 0 0 0 0 
transition add 1349 -1418 1807 -2070 1349 -2070 1807 -2084 0 1 0 0 0 0 IR0='0' AND IR15='0' AND IR14='0' AND ((IR13='0' AND IR12 = '0' AND IR11='0') OR (IR13 = '0' AND IR12 = '0' AND IR11='1') OR (IR13 = '0' AND IR12='1' AND IR11='0') OR (IR13='0' AND IR12='1' AND IR11='1') OR (IR13='1' AND IR12='0' AND IR11='0'))
graphic add 1900 -1686 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 1703 -1962 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 1506 -2239 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 1308 -2517 0 0 0 0 0 0 0 0 0 0 0 0 
transition add 3725 -2628 4183 -2812 3725 -2812 4183 -2826 0 24 0 0 0 0 IR15 = '0' AND IR14 = '1' AND IR13 = '1' AND IR12 = '1' AND IR11 = '1'
graphic add 2280 -1593 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 3336 -2330 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 4393 -3068 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 5450 -3807 0 0 0 0 0 0 0 0 0 0 0 0 
transition add 3325 -2086 3783 -2322 3325 -2322 3783 -2336 0 14 0 0 0 0 IR15 = '0' AND IR14 = '1' AND IR13 = '0' AND IR12 = '0' AND IR11 = '1' AND IR0='1'
graphic add 2286 -1562 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 3124 -2031 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 3962 -2500 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 4801 -2971 0 0 0 0 0 0 0 0 0 0 0 0 
transition add 1500 -2410 1958 -2594 1500 -2594 1958 -2608 0 27 0 0 0 0 IR15 = '0' AND IR14 = '1' AND IR13 = '0' AND IR12 = '0' AND IR11 = '0'
graphic add 2052 -1908 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 1935 -2205 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 1818 -2503 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 1701 -2801 0 0 0 0 0 0 0 0 0 0 0 0 
transition add 3940 -2007 4398 -2191 3940 -2191 4398 -2205 0 3 0 0 0 0 IR15 = '0' AND IR14 = '0' AND IR13 = '1' AND IR12 = '1' AND IR11 = '1'
graphic add 2294 -1511 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 3332 -1848 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 4370 -2185 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 5409 -2523 0 0 0 0 0 0 0 0 0 0 0 0 
transition add 5050 -1847 5508 -2083 5050 -2083 5508 -2097 0 21 0 0 0 0 IR0 = '1' AND IR15 = '0' AND IR14 = '0' AND IR13 = '1' AND IR12 = '0' AND IR11 = '0'
graphic add 2301 -1446 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 3548 -1690 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 4795 -1934 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 6042 -2178 0 0 0 0 0 0 0 0 0 0 0 0 
transition add 5275 -1396 5733 -1580 5275 -1580 5733 -1594 0 26 0 0 0 0 IR15 = '0' AND IR14 = '1' AND IR13 = '1' AND IR12 = '0' AND IR11 = '1'
graphic add 2307 -1362 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 4071 -1455 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 5835 -1549 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 7600 -1643 0 0 0 0 0 0 0 0 0 0 0 0 
transition add 4396 -1590 4854 -1814 4396 -1814 4854 -1828 0 8 0 0 0 0 IR15 = '0' AND IR14 = '1' AND IR13 = '1' AND IR12 = '0' AND IR11 = '0'
graphic add 2305 -1399 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 3786 -1556 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 5268 -1713 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 6750 -1871 0 0 0 0 0 0 0 0 0 0 0 0 
transition add 4350 -493 4808 -1093 4350 -1093 4808 -1107 0 29 0 0 0 0 IR15 = '0' AND IR14 = '1' AND IR13 = '0' AND IR12 = '1' AND IR11 = '1' AND (RES15 = '1' OR RES14 = '1' OR RES13 = '1' OR RES12 = '1' OR RES11 = '1' OR RES10 = '1' OR RES9 = '1' OR RES8 = '1' OR RES7 = '1' OR RES6 = '1' OR RES5 = '1' )
graphic add 2307 -1330 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 3505 -1033 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 4703 -736 0 0 0 0 0 0 0 0 0 0 0 0 
graphic add 5902 -439 0 0 0 0 0 0 0 0 0 0 0 0 
transition add 2250 -200 2708 -800 2250 -800 2708 -814 0 18 0 0 0 0  IR15 = '0' AND IR14 = '1' AND IR13 = '0' AND IR12 = '1' AND IR11 = '0' AND (RES15 = '1' OR RES14 = '1' OR RES13 = '1' OR RES12 = '1' OR RES11 = '1' OR RES10 = '1' OR RES9 = '1' OR RES8 = '1' OR RES7 = '1' OR RES6 = '1' OR RES5 = '1' )
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graphic add 2538 -983 0 0 0 0 0 0 0 0 0 0 0 0 
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graphic add 3000 -392 0 0 0 0 0 0 0 0 0 0 0 0 
transition add 2700 -648 3158 -1300 2700 -1300 3158 -1314 0 19 0 0 0 0 IR15 = '0' AND IR14 = '1' AND IR13 = '0' AND IR12 = '1' AND IR11 = '0' AND RES15 = '0' AND RES14 = '0' AND RES13 = '0' AND RES12 = '0' AND RES11 = '0' AND RES10 = '0' AND RES9 = '0' AND RES8 = '0' AND RES7 = '0' AND RES6 = '0' AND RES5 = '0'                
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transition add 2650 -2200 3108 -2488 2650 -2488 3108 -2502 0 6 0 0 0 0 IR15 = '0' AND IR14 = '0' AND IR13 = '1' AND ( (IR12 = '1' AND IR11 = '0') OR (IR12 = '0' AND IR11= '1'))
graphic add 2212 -1799 0 0 0 0 0 0 0 0 0 0 0 0 
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state select 0 0 0 0 0 0 0 0 0 11 0 0 0 0 
transition add 1650 -3380 2108 -4552 1650 -4552 2108 -4566 0 9 0 0 0 0 InterruptWait15 = '0' AND InterruptWait14 = '0' AND InterruptWait13 = '0' AND InterruptWait12 = '0' AND InterruptWait11 = '0' AND InterruptWait10 = '0' AND InterruptWait9 = '0'  AND InterruptWait8 = '0' AND InterruptWait7 = '0' AND InterruptWait6 = '0' AND InterruptWait5 = '0' AND InterruptWait4 = '0' AND InterruptWait3 = '0' AND InterruptWait2 = '0' AND InterruptWait1 = '0' AND InterruptWait0 = '0'
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graphic add 1220 -1950 0 0 0 0 0 0 0 0 0 0 0 0 
transition add 1599 -6624 2057 -7536 1599 -7536 2057 -7550 0 12 0 0 0 0 InterruptWait15 = '1' OR InterruptWait14 = '1' OR InterruptWait13 = '1' OR InterruptWait12 = '1' OR InterruptWait11 = '1' OR InterruptWait10 = '1' OR InterruptWait9 = '1' OR InterruptWait8 = '1' OR InterruptWait7 = '1' OR InterruptWait6 = '1' OR InterruptWait5 = '1' OR InterruptWait4 = '1' OR InterruptWait3 = '1' OR InterruptWait2 = '1' OR InterruptWait1 = '1' OR InterruptWait0 = '1'
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state select 0 0 0 0 0 0 0 0 0 31 0 0 0 0 
transition add 155 -98 613 -178 155 -178 613 -178 0 23 0 0 0 0 RESET
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