//	this verilog file dictates the behavior of our processor's ALU.
//based on the value of the ALUOperation, the ALU will either add, subtract, and, or, or invert.

module ALU(DataA, DataB, ALUOperation, DataOut);

input [2:0] ALUOperation;
input [15:0] DataA, DataB;		//operands for the ALU operation
output [15:0] DataOut;			   //16-bit output of ALU
wire [15:0] F0, F1, F2, F3, F4;	//temporary valuyes later to be selected for DataOut
reg [15:0] DataOut;
		  
//for ALUop = 000, add

assign F0[15:0] = DataA[15:0] + DataB[15:0];	//later on we might try to deal with overflow
						// for add and subtract
//for ALUop = 001, subtract
assign F1[15:0] = DataA[15:0] - DataB[15:0];

//for ALUop = 010, and
assign F2[15:0] = DataA[15:0] && DataB[15:0];

//for ALUop = 011, or
assign F3[15:0] = DataA[15:0] || DataB[15:0];

//for ALUop = 100, invert
assign F4[15:0] = ~DataA[15:0];

always
begin
//setting output 
	case (ALUOperation)
	0:		begin DataOut<=F0; end
	1:		begin DataOut<=F1; end
	2:		begin DataOut<=F2; end
	3:		begin DataOut<=F3; end
	4:		begin DataOut<=F4; end
	default: 	begin DataOut<=F4; end		//? Do we want something specific here?
	endcase

end

endmodule