Each of our components (besides registers and muxes) are listed here in Zip files. Zip files include a the component designed in verilog and a test bench created by us.

ALU
variable shifter
"ByteRam". A memory file borrowed from Professor Merkle
concatination
control unit
register file
all components hooked together(miniprocessor)
control unit
register file
concatination
control unit
zero checker