// C:\XILINX\PROJECTS\TRIPENT\STATE2.v
// Verilog created by Xilinx's StateCAD 5.1i
// Fri Oct 31 00:05:43 2003
// This Verilog code (for use with Xilinx XST) was generated using:
// binary encoded state assignment with structured code format.
// Minimization is enabled, implied else is enabled,
// and outputs are speed optimized.
`timescale 1s/1s
module shell_state2(CLK,OPCODE0,OPCODE1,OPCODE2,OPCODE3,OPCODE4,OPCODE5,
OPCODE15,STATUS0,STATUS1,STATUS2,STATUS3,STATUS4,STATUS5,STATUS6,STATUS7,
STATUS8,STATUS9,STATUS10,STATUS11,STATUS12,STATUS13,STATUS14,STATUS15,
ALUControl0,ALUControl1,ALUControl2,ALUSrcA,ALUSrcB,CRWrite,EPCWrite,IRWrite,
MemAddrSelect0,MemAddrSelect1,MemRead,MemWrite,PCWrite,PCWriteSelect0,
PCWriteSelect1,PCWriteSelect2,RegRead,RegWrite,ShiftDirection,StatusInputSel0
,StatusInputSel1,StatusService0,StatusService1,StatusService2,StatusService3,
WriteDataSel0,WriteDataSel1,WriteRegSelect);
input CLK;
input OPCODE0,OPCODE1,OPCODE2,OPCODE3,OPCODE4,OPCODE5,OPCODE15,STATUS0,
STATUS1,STATUS2,STATUS3,STATUS4,STATUS5,STATUS6,STATUS7,STATUS8,STATUS9,
STATUS10,STATUS11,STATUS12,STATUS13,STATUS14,STATUS15;
output ALUControl0,ALUControl1,ALUControl2,ALUSrcA,ALUSrcB,CRWrite,EPCWrite,
IRWrite,MemAddrSelect0,MemAddrSelect1,MemRead,MemWrite,PCWrite,PCWriteSelect0
,PCWriteSelect1,PCWriteSelect2,RegRead,RegWrite,ShiftDirection,
StatusInputSel0,StatusInputSel1,StatusService0,StatusService1,StatusService2,
StatusService3,WriteDataSel0,WriteDataSel1,WriteRegSelect;
reg [2:0] ALUControl;
reg [1:0] MemAddrSelect;
reg [2:0] PCWriteSelect;
reg [1:0] StatusInputSel;
reg [3:0] StatusService;
reg [1:0] WriteDataSel;
reg ALUControl0,next_ALUControl0,ALUControl1,next_ALUControl1,ALUControl2,
next_ALUControl2,ALUSrcA,next_ALUSrcA,ALUSrcB,next_ALUSrcB,CRWrite,
next_CRWrite,EPCWrite,next_EPCWrite,IRWrite,next_IRWrite,MemAddrSelect0,
next_MemAddrSelect0,MemAddrSelect1,next_MemAddrSelect1,MemRead,next_MemRead,
MemWrite,next_MemWrite,PCWrite,next_PCWrite,PCWriteSelect0,
next_PCWriteSelect0,PCWriteSelect1,next_PCWriteSelect1,PCWriteSelect2,
next_PCWriteSelect2,RegRead,next_RegRead,RegWrite,next_RegWrite,
ShiftDirection,next_ShiftDirection,StatusInputSel0,next_StatusInputSel0,
StatusInputSel1,next_StatusInputSel1,StatusService0,next_StatusService0,
StatusService1,next_StatusService1,StatusService2,next_StatusService2,
StatusService3,next_StatusService3,WriteDataSel0,next_WriteDataSel0,
WriteDataSel1,next_WriteDataSel1,WriteRegSelect,next_WriteRegSelect;
reg [4:0] sreg;
reg [4:0] next_sreg;
`define ADD 5'b11111
`define AND_OP 5'b11110
`define CLI 5'b11101
`define CMPE0 5'b11100
`define CMPE1 5'b11011
`define CMPL0 5'b11010
`define CMPL1 5'b11001
`define EXC0 5'b11000
`define EXC1 5'b10111
`define INSTRUCTION 5'b10110
`define J 5'b10101
`define JAL 5'b10100
`define JNZ 5'b10011
`define JZ 5'b10010
`define LIRWRITE 5'b10001
`define LW0 5'b10000
`define LW1 5'b01111
`define OR_OP 5'b01110
`define REGLOAD 5'b01101
`define REGSTORE 5'b01100
`define RFI 5'b01011
`define SHL 5'b01010
`define SHR 5'b01001
`define START 5'b01000
`define STI 5'b00111
`define SUB 5'b00110
`define SW 5'b00101
`define XOR_OP 5'b00100
always @(posedge CLK)
begin
sreg = next_sreg;
ALUSrcA = next_ALUSrcA;
ALUSrcB = next_ALUSrcB;
CRWrite = next_CRWrite;
EPCWrite = next_EPCWrite;
IRWrite = next_IRWrite;
MemRead = next_MemRead;
MemWrite = next_MemWrite;
PCWrite = next_PCWrite;
RegRead = next_RegRead;
RegWrite = next_RegWrite;
ShiftDirection = next_ShiftDirection;
WriteRegSelect = next_WriteRegSelect;
ALUControl2 = next_ALUControl2;
ALUControl1 = next_ALUControl1;
ALUControl0 = next_ALUControl0;
MemAddrSelect1 = next_MemAddrSelect1;
MemAddrSelect0 = next_MemAddrSelect0;
PCWriteSelect2 = next_PCWriteSelect2;
PCWriteSelect1 = next_PCWriteSelect1;
PCWriteSelect0 = next_PCWriteSelect0;
StatusInputSel1 = next_StatusInputSel1;
StatusInputSel0 = next_StatusInputSel0;
StatusService3 = next_StatusService3;
StatusService2 = next_StatusService2;
StatusService1 = next_StatusService1;
StatusService0 = next_StatusService0;
WriteDataSel1 = next_WriteDataSel1;
WriteDataSel0 = next_WriteDataSel0;
end
always @ (sreg or OPCODE0 or OPCODE1 or OPCODE2 or OPCODE3 or OPCODE4 or
OPCODE15 or STATUS0 or STATUS14 or ALUControl or MemAddrSelect or
PCWriteSelect or StatusInputSel or StatusService or WriteDataSel)
begin
next_ALUControl0 = 0; next_ALUControl1 = 0; next_ALUControl2 = 0;
next_ALUSrcA = 0; next_ALUSrcB = 0; next_CRWrite = 0; next_EPCWrite = 1;
next_IRWrite = 0; next_MemAddrSelect0 = 0; next_MemAddrSelect1 = 0;
next_MemRead = 0; next_MemWrite = 0; next_PCWrite = 0; next_PCWriteSelect0 =
0; next_PCWriteSelect1 = 0; next_PCWriteSelect2 = 0; next_RegRead = 0;
next_RegWrite = 0; next_ShiftDirection = 0; next_StatusInputSel0 = 0;
next_StatusInputSel1 = 0; next_StatusService0 = 0; next_StatusService1 = 0;
next_StatusService2 = 0; next_StatusService3 = 0; next_WriteDataSel0 = 0;
next_WriteDataSel1 = 0; next_WriteRegSelect = 0;
ALUControl=3'h0; MemAddrSelect=2'h0; PCWriteSelect=3'h0;
StatusInputSel=2'h0; StatusService=4'h0; WriteDataSel=2'h0;
next_sreg=`ADD;
case (sreg)
`ADD : begin
next_sreg=`REGSTORE;
next_IRWrite=0;
next_ShiftDirection=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
next_RegWrite=1;
next_WriteRegSelect=1;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h3;
end
`AND_OP : begin
next_sreg=`REGSTORE;
next_IRWrite=0;
next_ShiftDirection=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
next_RegWrite=1;
next_WriteRegSelect=1;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h3;
end
`CLI : begin
next_sreg=`START;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
end
`CMPE0 : begin
next_sreg=`CMPE1;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
WriteDataSel= 'h0;
StatusService= 'h1;
StatusInputSel= 'h0;
end
`CMPE1 : begin
next_sreg=`START;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
end
`CMPL0 : begin
next_sreg=`CMPL1;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
WriteDataSel= 'h0;
StatusService= 'h1;
StatusInputSel= 'h1;
end
`CMPL1 : begin
next_sreg=`START;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
end
`EXC0 : begin
next_sreg=`EXC1;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
next_PCWrite=1;
ALUControl= 'h0;
MemAddrSelect= 'h0;
WriteDataSel= 'h0;
StatusService= 'h0;
StatusInputSel= 'h3;
PCWriteSelect= 'h2;
end
`EXC1 : begin
next_sreg=`START;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
end
`INSTRUCTION : begin
if ( ~OPCODE15 ) begin
next_sreg=`LIRWRITE;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
next_IRWrite=1;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
end
else begin
next_sreg=`REGLOAD;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
next_RegRead=1;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
end
end
`J : begin
next_sreg=`START;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
end
`JAL : begin
next_sreg=`J;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
next_PCWrite=1;
ALUControl= 'h0;
MemAddrSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
PCWriteSelect= 'h1;
end
`JNZ : begin
if ( STATUS0 ) begin
next_sreg=`J;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
next_PCWrite=1;
ALUControl= 'h0;
MemAddrSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
PCWriteSelect= 'h1;
end
if ( ~STATUS0 ) begin
next_sreg=`START;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
end
end
`JZ : begin
if ( STATUS0 ) begin
next_sreg=`START;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
end
if ( ~STATUS0 ) begin
next_sreg=`J;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
next_PCWrite=1;
ALUControl= 'h0;
MemAddrSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
PCWriteSelect= 'h1;
end
end
`LIRWRITE : begin
next_sreg=`START;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
end
`LW0 : begin
next_sreg=`LW1;
next_IRWrite=0;
next_ShiftDirection=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
next_RegWrite=1;
next_WriteRegSelect=1;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h2;
end
`LW1 : begin
next_sreg=`START;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
end
`OR_OP : begin
next_sreg=`REGSTORE;
next_IRWrite=0;
next_ShiftDirection=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
next_RegWrite=1;
next_WriteRegSelect=1;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h3;
end
`REGLOAD : begin
if ( OPCODE4 & OPCODE3 | OPCODE2 & OPCODE1 & OPCODE4 | OPCODE4 & ~OPCODE2
& ~OPCODE1 | ~OPCODE1 & OPCODE3 & ~OPCODE2 | OPCODE2 & OPCODE1 & OPCODE0 &
OPCODE3 ) begin
next_sreg=`REGLOAD;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
next_RegRead=1;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
end
if ( ~OPCODE4 & OPCODE3 & ~OPCODE2 & OPCODE1 & OPCODE0 ) begin
next_sreg=`SW;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
next_MemWrite=1;
ALUControl= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
MemAddrSelect= 'h2;
end
if ( ~OPCODE4 & ~OPCODE3 & ~OPCODE2 & OPCODE1 & ~OPCODE0 ) begin
next_sreg=`OR_OP;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
ALUControl= 'h2;
end
if ( ~OPCODE4 & ~OPCODE3 & ~OPCODE2 & ~OPCODE1 & OPCODE0 ) begin
next_sreg=`AND_OP;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
ALUControl= 'h4;
end
if ( ~OPCODE4 & ~OPCODE3 & ~OPCODE2 & OPCODE1 & OPCODE0 ) begin
next_sreg=`XOR_OP;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
ALUControl= 'h3;
end
if ( ~OPCODE4 & ~OPCODE3 & ~OPCODE2 & ~OPCODE1 & ~OPCODE0 ) begin
next_sreg=`ADD;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
ALUControl= 'h0;
end
if ( OPCODE4 & ~OPCODE3 & OPCODE2 & ~OPCODE1 & OPCODE0 ) begin
next_sreg=`SUB;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
ALUControl= 'h1;
end
if ( ~OPCODE4 & OPCODE3 & ~OPCODE2 & OPCODE1 & ~OPCODE0 ) begin
next_sreg=`LW0;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
next_MemRead=1;
ALUControl= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
MemAddrSelect= 'h2;
end
if ( ~OPCODE4 & OPCODE3 & OPCODE2 & ~OPCODE1 & OPCODE0 ) begin
next_sreg=`JNZ;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
end
if ( ~OPCODE4 & OPCODE3 & OPCODE2 & ~OPCODE1 & ~OPCODE0 ) begin
next_sreg=`JZ;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
end
if ( ~OPCODE4 & OPCODE3 & OPCODE2 & OPCODE1 & ~OPCODE0 ) begin
next_sreg=`JAL;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
next_RegWrite=1;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
end
if ( ~OPCODE4 & ~OPCODE3 & OPCODE2 & ~OPCODE1 & OPCODE0 ) begin
next_sreg=`SHR;
next_IRWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
next_ShiftDirection=1;
next_RegWrite=1;
next_WriteRegSelect=1;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h1;
end
if ( ~OPCODE4 & ~OPCODE3 & OPCODE2 & ~OPCODE1 & ~OPCODE0 ) begin
next_sreg=`SHL;
next_IRWrite=0;
next_ShiftDirection=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
next_RegWrite=1;
next_WriteRegSelect=1;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h1;
end
if ( OPCODE4 & ~OPCODE3 & OPCODE2 & ~OPCODE1 & ~OPCODE0 ) begin
next_sreg=`RFI;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
next_PCWrite=1;
ALUControl= 'h0;
MemAddrSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
PCWriteSelect= 'h0;
end
if ( OPCODE4 & ~OPCODE3 & ~OPCODE2 & OPCODE1 & OPCODE0 ) begin
next_sreg=`STI;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
WriteDataSel= 'h0;
StatusInputSel= 'h2;
StatusService= 'h2;
end
if ( OPCODE4 & ~OPCODE3 & ~OPCODE2 & OPCODE1 & ~OPCODE0 ) begin
next_sreg=`CLI;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
WriteDataSel= 'h0;
StatusInputSel= 'h3;
StatusService= 'h3;
end
if ( ~OPCODE4 & ~OPCODE3 & OPCODE2 & OPCODE1 & OPCODE0 ) begin
next_sreg=`CMPL0;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
ALUControl= 'h1;
end
if ( ~OPCODE4 & ~OPCODE3 & OPCODE2 & OPCODE1 & ~OPCODE0 ) begin
next_sreg=`CMPE0;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
ALUControl= 'h1;
end
end
`REGSTORE : begin
next_sreg=`START;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
end
`RFI : begin
next_sreg=`START;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
end
`SHL : begin
next_sreg=`START;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
end
`SHR : begin
next_sreg=`START;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
end
`START : begin
if ( ~STATUS14 ) begin
next_sreg=`INSTRUCTION;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_MemWrite=0;
next_EPCWrite=1;
next_MemRead=1;
next_ALUSrcA=1;
next_ALUSrcB=1;
next_PCWrite=1;
next_CRWrite=1;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
MemAddrSelect= 'h1;
PCWriteSelect= 'h3;
ALUControl= 'h0;
end
if ( STATUS14 ) begin
next_sreg=`EXC0;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
next_MemRead=1;
next_EPCWrite=0;
ALUControl= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
MemAddrSelect= 'h0;
end
end
`STI : begin
next_sreg=`START;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
end
`SUB : begin
next_sreg=`REGSTORE;
next_IRWrite=0;
next_ShiftDirection=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
next_RegWrite=1;
next_WriteRegSelect=1;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h3;
end
`SW : begin
next_sreg=`START;
next_IRWrite=0;
next_WriteRegSelect=0;
next_ShiftDirection=0;
next_RegWrite=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h0;
end
`XOR_OP : begin
next_sreg=`REGSTORE;
next_IRWrite=0;
next_ShiftDirection=0;
next_RegRead=0;
next_PCWrite=0;
next_MemWrite=0;
next_MemRead=0;
next_EPCWrite=1;
next_CRWrite=0;
next_ALUSrcB=0;
next_ALUSrcA=0;
next_RegWrite=1;
next_WriteRegSelect=1;
ALUControl= 'h0;
MemAddrSelect= 'h0;
PCWriteSelect= 'h0;
StatusInputSel= 'h0;
StatusService= 'h0;
WriteDataSel= 'h3;
end
endcase
next_ALUControl2 = ALUControl[2];
next_ALUControl1 = ALUControl[1];
next_ALUControl0 = ALUControl[0];
next_MemAddrSelect1 = MemAddrSelect[1];
next_MemAddrSelect0 = MemAddrSelect[0];
next_PCWriteSelect2 = PCWriteSelect[2];
next_PCWriteSelect1 = PCWriteSelect[1];
next_PCWriteSelect0 = PCWriteSelect[0];
next_StatusInputSel1 = StatusInputSel[1];
next_StatusInputSel0 = StatusInputSel[0];
next_StatusService3 = StatusService[3];
next_StatusService2 = StatusService[2];
next_StatusService1 = StatusService[1];
next_StatusService0 = StatusService[0];
next_WriteDataSel1 = WriteDataSel[1];
next_WriteDataSel0 = WriteDataSel[0];
end
endmodule
module state2(ALUControl,MemAddrSelect,OPCODE,PCWriteSelect,STATUS,
StatusInputSel,StatusService,WriteDataSel,CLK,OPCODE15,ALUSrcA,ALUSrcB,
CRWrite,EPCWrite,IRWrite,MemRead,MemWrite,PCWrite,RegRead,RegWrite,
ShiftDirection,WriteRegSelect);
output [2:0] ALUControl;
output [1:0] MemAddrSelect;
input [5:0] OPCODE;
output [2:0] PCWriteSelect;
input [15:0] STATUS;
output [1:0] StatusInputSel;
output [3:0] StatusService;
output [1:0] WriteDataSel;
input CLK;
input OPCODE15;
output ALUSrcA,ALUSrcB,CRWrite,EPCWrite,IRWrite,MemRead,MemWrite,PCWrite,
RegRead,RegWrite,ShiftDirection,WriteRegSelect;
wire [2:0] ALUControl;
wire [1:0] MemAddrSelect;
wire [5:0] OPCODE;
wire [2:0] PCWriteSelect;
wire [15:0] STATUS;
wire [1:0] StatusInputSel;
wire [3:0] StatusService;
wire [1:0] WriteDataSel;
wire CLK;
wire OPCODE15;
wire ALUSrcA,ALUSrcB,CRWrite,EPCWrite,IRWrite,MemRead,MemWrite,PCWrite,
RegRead,RegWrite,ShiftDirection,WriteRegSelect;
shell_state2 part1(.CLK(CLK),.OPCODE0(OPCODE[0]),.OPCODE1(OPCODE[1]),
.OPCODE2(OPCODE[2]),.OPCODE3(OPCODE[3]),.OPCODE4(OPCODE[4]),.OPCODE5(
OPCODE[5]),.OPCODE15(OPCODE15),.STATUS0(STATUS[0]),.STATUS1(STATUS[1]),
.STATUS2(STATUS[2]),.STATUS3(STATUS[3]),.STATUS4(STATUS[4]),.STATUS5(
STATUS[5]),.STATUS6(STATUS[6]),.STATUS7(STATUS[7]),.STATUS8(STATUS[8]),
.STATUS9(STATUS[9]),.STATUS10(STATUS[10]),.STATUS11(STATUS[11]),.STATUS12(
STATUS[12]),.STATUS13(STATUS[13]),.STATUS14(STATUS[14]),.STATUS15(STATUS[15])
,.ALUControl0(ALUControl[0]),.ALUControl1(ALUControl[1]),.ALUControl2(
ALUControl[2]),.ALUSrcA(ALUSrcA),.ALUSrcB(ALUSrcB),.CRWrite(CRWrite),
.EPCWrite(EPCWrite),.IRWrite(IRWrite),.MemAddrSelect0(MemAddrSelect[0]),
.MemAddrSelect1(MemAddrSelect[1]),.MemRead(MemRead),.MemWrite(MemWrite),
.PCWrite(PCWrite),.PCWriteSelect0(PCWriteSelect[0]),.PCWriteSelect1(
PCWriteSelect[1]),.PCWriteSelect2(PCWriteSelect[2]),.RegRead(RegRead),
.RegWrite(RegWrite),.ShiftDirection(ShiftDirection),.StatusInputSel0(
StatusInputSel[0]),.StatusInputSel1(StatusInputSel[1]),.StatusService0(
StatusService[0]),.StatusService1(StatusService[1]),.StatusService2(
StatusService[2]),.StatusService3(StatusService[3]),.WriteDataSel0(
WriteDataSel[0]),.WriteDataSel1(WriteDataSel[1]),.WriteRegSelect(
WriteRegSelect));
endmodule