/*********************************************************/
// MODULE:			RegFile
//
// FILE NAME:		RegFile.v
// VERSION:			1.0
// DATE:				Feb 9, 2003
// AUTHOR:			Koushik Subramanian
//
// DESCRIPTION:	This module defines a register file with 
//                thirty-two 16-bit registers, two read ports, 
//                and one write port.  
//
/*********************************************************/

/*********************************************************/
// MODULE:			RegFile
//
// FILE NAME:		RegFile.v
// VERSION:			1.1
// DATE:				Created Feb 9, 2003
//                Modified Nov 15, 2003 by Larry Merkle
//                - "Unregistered" ReadDataN to eliminate
//                  the clock cycle delay between changing 
//                  ReadRegN and seeing the effect on ReadDataN
// AUTHOR:			Larry Merkle
//
// DESCRIPTION:	This module defines a register file with 
//                eight 16-bit registers, two read ports, 
//                and one write port.  
//
/*********************************************************/
module RegFile(
   ReadReg1,
   ReadReg2,
   WriteReg,
   WriteData,
   RegWrite,
   ReadData1,               
   ReadData2,
	IRIn,
	IROut,
	IRWriteSelect,
   CLK);

// Definitions

parameter NUM_REGS = 32;
`define ADDR_SZ 5
`define REG_WIDTH 16

// Inputs

input [`ADDR_SZ-1:0] ReadReg1;
input [`ADDR_SZ-1:0] ReadReg2;
input [`ADDR_SZ-1:0] WriteReg;
input [`REG_WIDTH-1:0] WriteData;
input [`REG_WIDTH-1:0] IRIn;
input RegWrite;
input CLK;

// Outputs

output [`REG_WIDTH-1:0] ReadData1;
output [`REG_WIDTH-1:0] ReadData2;
output [`REG_WIDTH-1:0] IROut;
output IRWriteSelect;

// Signals

wire [`REG_WIDTH-1:0] ReadData1;
wire [`REG_WIDTH-1:0] ReadData2;
wire [`REG_WIDTH-1:0] IROut;
reg IRWriteSelect;

// The registers

reg [`REG_WIDTH-1:0] Reg [NUM_REGS-1:0];


assign IROut = Reg[28];
//assign IRWriteSelect = (WriteReg == 28);
assign ReadData1 = Reg[ ReadReg1 ];
assign ReadData2 = Reg[ ReadReg2 ];

// Operation

integer i;

// HACK!
initial begin
	for(i = 0; i < 32; i = i + 1) begin
		Reg[ i ] = 16'b0;
	end
	Reg[ 31] = 16'd1052;	// End of memory
end

always @ ( posedge CLK ) begin
	IRWriteSelect <= (WriteReg == 28);
	Reg[ 28 ] = IRIn;
  	if ( RegWrite == 1)
    		Reg[ WriteReg ] = WriteData;
end

endmodule


/*
module RegFile(
   ReadReg1,
   ReadReg2,
   WriteReg,
   WriteData,
   RegWrite,
	IRWriteSelect,
   ReadData1,               
   ReadData2,
	IRIn,
	IROut,
	Reset,
   CLK);

// Definitions

parameter NUM_REGS = 32;
`define ADDR_SZ 3
`define REG_WIDTH 16

// Inputs

input [4:0] ReadReg2;
input [4:0] ReadReg1;
input [4:0] WriteReg;
input [15:0] WriteData;
input [15:0] IRIn;
input RegWrite;
input Reset;
input CLK;


// Outputs

output [15:0] ReadData1;
output [15:0] ReadData2;
output IRWriteSelect;
output [15:0] IROut;

// Signals


wire [`REG_WIDTH-1:0] ReadData1;
wire [`REG_WIDTH-1:0] ReadData2;


// The registers

reg [15:0] Reg [31:0];


integer out1;
integer out2;

integer irw;

integer counter;

assign ReadData1 = Reg[ ReadReg1 ];
assign ReadData2 = Reg[ ReadReg2 ];
assign IRWriteSelect = (WriteReg == 28);
assign IROut = Reg[28];

always @ ( posedge CLK or posedge Reset ) begin	

		if (Reset == 1) begin
			for(counter=0; counter < 32; counter = counter + 1) begin
				Reg[ counter ] = 16'b0;
			end
		end
	
		else begin			
//			irw = 0;
			Reg[28] = IRIn;
//			out1 = Reg[ ReadReg1 ];
//			out2 = Reg[ ReadReg2 ];

			if ( RegWrite )
				Reg[ WriteReg ] = WriteData;

//			if ( WriteReg == 28) 
//				irw = 1;		
		end
end

endmodule
*/