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Computer Architecture I |
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Group 2-5 Ben Barnett - Tim Cline - Peter Fine - Tom Aigner - Branden Neufeld |
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Memo 5 10/31/03 To: Professor Chidanandan From: Group 2-5 Date: October 31, 2003 Subject: Milestone 5 ___________________________________________________________________________________________________________________________ Professor Chidanandan:
Milestone 5 has been completed. We have created all of the components necessary to implement our datapath in Xilinx. Exhausted testing has been performed on each component revealing only minor errors such as a misplaced quote or semicolon in our control unit implementation. We used testbench waveforms to test all components except the control unit, including four tests of each instruction for the ALU. All Xilinx files have been posted in our turnin folder and our webpage has been updated. We plan to go through each of the past milestones so that we can make any corrections necessary while improving their appearance.
We believe that we have fulfilled the requirements for milestone 5 through the completion of component implementation and testing in Xilinx.
Memo 4 10/24/03 To: Professor Chidanandan From: Group 2-5 Date: October 24, 2003 Subject: Milestone 4 ____________________________________________________________________________________________________________________________ Professor Chidanandan:
Milestone 4 has been completed and includes the component specification and testing. We have also implemented many of our components in Xilinx. The team webpage has been updated to include our latest Design Documentation along with the Xilinx files for some of our components. We have had few difficulties while designing components, however, we have not yet decided whether or not to implement multiplication and division within our ALU. We are still considering whether we want the Hi and Lo registers required for such operations. This milestone also includes some tests we can perform to ensure that our components are functioning properly. In Xilinx we should be able to confirm that each component operates as it should. We believe that we have fulfilled the requirements for milestone 4 through the completion of component implementation and testing. In some aspects, we are ahead of the game since we have implemented some of our components in Xilinx.
Memo 3 10/10/03 To: Professor Chidanandan From: Group 2-5 Date: October 10, 2003 Subject: Milestone 3 ____________________________________________________________________________________________________________________________ Professor Chidanandan: Milestone 3 has been completed and includes the data path for our RTL instructions. The group webpage has been updated to include our latest work. So far we have not had very many difficulties designing our data path from our RTL instructions. However, we are a little unsure of how to specify in our data path how we handle reading from memory two times in order to support our 24-bit system. We have included components for handling exceptions and interrupts. Along with the data path, we have included an English description of all the control signals used in our data path design. This description lists each control signal and provides a short description of how it functions in our design. We also have completed a finite state machine document for our RTL instructions which maps the state of the system through each clock cycle for each RTL instruction. We believe that we have completed the requirements for milestone 3, including the data path, finite state machine diagram and the English description of components.
Memo 2 10/7/03 We have completed milestone 2 which includes the RTL for each of our commands and the components needed for the RTL. We have redesigned our webpage to facilitate navigation to our milestone documents. One difficulty we have addressed is reading from memory 2 times in order to use our 24-bit system on 16-bit hardware. This required us to use 2 steps in our RTL where in one step we added 2 to the program counter and in the second step we added 1. We reorganized the machine code and commands from milestone 1, making it more understandable. We made a change to the location of the function code by placing it next to the opcode for easy reading. We have also increased the functionality of the function code by using it as an alternate register in immediate and branch type commands. We believe we have the capability to implement Euclids algorithm, handle interrupts, read from the input, write to the output and wait for one of the interrupts to occur. The requirements for milestone 2 have been fulfilled with the exception of testing.
Memo 1 9/29/03 Our group has completed milestone one. We have decided to use a 24 bit system that includes 16 operators, 16 general purpose registers and 10 special registers. The webpage for our project has been implemented and clearly displays our progress. It is here that you can find the programming manual for our assembly language. We elected to use only 16 operators because we felt that any other operators that we may need could be derived from our selected operators. Each operator uses a 4-bit opcode and has 4-bits for registers in case we need to read 16-bit immediate values. We believe that the requirements of milestone one have been fulfilled to the degree of assigning registers and operators along with ensuring that the assembly language can handle basic programming tasks.
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