J Offset Test Case: Preconditions: PC = 0x0000 Mem[0x0000] = 1011000000101010 = J 42 Postconditions: PC = (42+1)*2 = 86 = 0x0056 IR = Mem[0x0000] = 1011000000101010 PC = PC + 2 = 0x0000 + 0x2 = 0x0002 A = Reg[IR[11-8]] = Reg[0000] = $0 B = Reg[IR[7-4]] = Reg[1010] = $a0 if (IR[15-12] = 1011 = 11 == 11) PC = PC + shift-left-1(sign-extend(IR[7-0])) = 0x0002 + 0x0054 = 0x0056 --------------------------------------- MASKI Test Case: Preconditions: IEB = 0; PC = 0x0000; Mem[0x0000] = 1100000000000000 = 0xC000; Postconditions: PC = 0x0002; IEB = 1; IR = Mem[PC] = Mem[0x0000] = 0xC000; PC = PC + 2 = 0x0000 + 0x0002 = 0x0002; A = Reg[IR[11-8]] = Reg[0x0] = $0 B = Reg[IR[7-4]] = Reg[0x0] = $0 if ( IR[15-12] = 1100 = 12 == 12) IEB = not(IEB) = not(0) = 1; --------------------------------------- RFI Test Case: Preconditions: PC = 0x5000; Mem[PC] = 1101000000000000 EPC = 0x0000; Postconditions: PC = 0x0000; IR = Mem[PC] = Mem[0x5000] = 0xD000; PC = PC + 2 = 0x5000 + 0x0002 = 0x5002; A = Reg[IR[11-8]] = Reg[0x0] = $0 B = Reg[IR[7-4]] = Reg[0x0] = $0 if ( IR[15-12] = 1100 = 13 == 13) PC = EPC = 0x0000; --------------------------------------- $t0 = 6, $t1 = 4 add $s0, $t0, $t1 0000 0010 0011 0110 1) IR = 0000 0010 0011 0110 PC = PC + 2 2) A = 0010 B = 0011 if(0000 == 0) [true] 3) C = Reg[0010] + Reg[0011] = 6 + 4 = 10 4) Reg[0110] = C = 10 --------------------------------------- $t0 = 6, $t1 = 4 sub $s0, $t0, $t1 0001 0010 0011 0110 1) IR = 0000 0010 0011 0110 PC = PC + 2 2) A = 0010 B = 0011 if(0001 == 1) [true] 3) C = Reg[0010] - Reg[0011] = 6 - 4 = 2 4) Reg[0110] = C = 2 --------------------------------------- $t0 = 6, $t1 = 4 slt $s0, $t0, $t1 0010 0010 0011 0110 1) IR = 0000 0010 0011 0110 PC = PC + 2 2) A = 0010 B = 0011 if(0010 == 2) [true] 3) C = Reg[0010] - Reg[0011] = 6 - 4 = 2 = 0000 0000 0000 0010 4) Reg[0110] = SRL15 || C = 0000 0000 0000 0000 = 0 --------------------------------------- $t0 = 4, $t1 = 6 slt $s0, $t0, $t1 0010 0010 0011 0110 1) IR = 0000 0010 0011 0110 PC = PC + 2 2) A = 0010 B = 0011 if(0010 == 2) [true] 3) C = Reg[0010] - Reg[0011] = 4 - 6 = -2 = 1111 1111 1111 1110 4) Reg[0110] = SRL15 || C = 0000 0000 0000 0001 = 1 --------------------------------------- LW: before 1 MEMORY@PC=4210 PC=3a20 IR=xxxx after 1 IR=4210 PC=3a22 before 2 Reg[IR[11-8]]=000c Reg[IR[7-4]]=0010 A =xxxx B =xxxx IR=4210 after 2 A =000c B =0010 IR=4210 before 3 MEMORY[0010]=xxxx A =0010 B =000c after 3 Reg[0010]=MEMORY[000c] --------------------------------------- SW: before 1 MEMORY@PC=3210 PC=3a20 IR=xxxx after 1 IR=3210 PC=3a22 before 2 Reg[IR[11-8]]=000c Reg[IR[7-4]]=0010 A =xxxx B =xxxx IR=3210 after 2 A =000c B =0010 IR=3210 before 3 MEMORY[0010]=xxxx A =0010 B =000c after 3 MEMORY[0010]=000c --------------------------------------- LUI: before 1 MEMORY@PC=7210 IR=xxxx PC=3a20 after 1 IR=7210 PC=3a22 before 2 Reg[IR[11-8]]=000c Reg[IR[7-4]]=0010 A=xxxx B=xxxx IR=7210 after 2 A=000c B=0010 before 3 IMM=xxxx IR[7-0]=0010 after 3 IMM=0010 before 4 reg[IR[11-8]]=xxxx IMM=0010 after 4 reg[IR[11-8]]=1000 increment pc and load instruction test and store load immediate to IMM load to reg IMM shifted 8 bits to left --------------------------------------- LLI before 1 IR=xxxx MEMORY@PC=8210 PC=3a20 after 1 IR=8210 PC=3a22 before 2 Reg[IR[11-8]]=000c Reg[IR[7-8]]=0010 A=xxxx B=xxxx IR=8210 after 2 A=000c B=0010 before 3 Reg[IR[11-8]]=xxxx IR[7-0]=0010 after 3 Reg[IR[11-8]]=0010 --------------------------------------- bez PC = 0x0004 Mem[0x0004] = 0101 0000 0100 1000 After 1: PC = 0x0006 IR = 0101 0000 0100 1000 After 2: A = 0 B = 6 After 3: A = 0, so After 4: PC = 0x0006 + binary(0100 1000) = 0x004e --------------------------------------- jal PC = 0x0004 Mem[0x0004] = 1010 0011 0101 1000 After 1: PC = 0x0006 IR = 1010 0011 0101 1000 After 2: A = 0 B = 6 After 3: Mem[Reg[0001]] = 0x0006 After 4: PC = 0x0058 --------------------------------------- jr PC = 0x0004 Mem[0x0004] = 1001 0011 0101 1000 After 1: PC = 0x0006 IR = 1001 0011 0101 1000 After 2: A = 3 B = 6 After 3: PC = Mem[Reg[IR[11-8]]]