Milestone 1
Files
demo of final program written in C++
C++ source code
Assembly Language Instructions
Machine Language Instructions
Design Journal
we decided on these registers based on the code we wrote. we stayed under 8 registers so we could use 3 bit addresses for the registers
Registers:$s0,$dr,$ra,$t0,$a0,$al,$v0,$0
our original implementation called for a very miniscule instruction set using NAND to implement many of the instructions as pseudoinstructions.
even still, we had reached 9 instructions we needed and had to go with a 4 bit opcode. we decided to split this up, however with the opcode
defining the instruction type and the function field defining the instruction.
Instructions:
note, opcodes define the instruction type, and func field specifies instruction
opcode 00:SLT,ADD,SUB
opcode 01:ADDI,LW,SW,LUI
opcode 10:JAL,J
opcode 11:BEQ
Instruction Types:
we split our instruction types into 4 different formats and differentiated them
by opcode. this allows for simple grouping of instructions by arguments.
we made opcode 11 without a funct field. this was done to expand the
offset field to 8 bits for greater range on the BEQ instruction.
However, upon attempting to implement this scheme in binary, we found the lack of registers to be a harsh limitation
as well as problems with the 6-bit immediates on some of our instructions, making it extremely difficult to
load long addresses into registers. To fix this, we decided to use 4 bits per register, raising our potential
total to 16. To alleviate problems with the BEQ instruction, we replaced it with the BEZ (branch equal to zero) instruction.
As it only uses a single register, it allows for a sizeable offset even with the increased register bits.
In addition, we added a LLI (load lower immediate) instruction to ease the loading of long addresses. Finally,
we removed the ADDI instruction as it would not be of much use with the decreased immediate size.
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