Term Project

Computer Architecture

Term Project:
Group 1-4
Team Members:
Adam Westhusing, Geoffrey Ulman, Jason Hochstedler, Gabe Golcher, Jeremy Fox
Send Mail to Whole Group

Note: This website contains the most up-to-date documents;
please refer here for team progress...

News:
-Still working on FPGA implementation
-Work on Powerpoint slides and send to Gabe

Final and Continuing Documents:
(For Final Handin at End of Quarter)

Constantly updated error correction log: Error-Change Tracking Log.doc

Component Testing Documentation: Component Implementation and Testing.doc

Component Specifications: Component Specification.doc

Data Path and Control Design: Data Path and Control Design.doc

Current Version of Assembly Language Specifications: Assembly Language Specifications V6.doc

Current Version of Machine Language Specifications: Machine Language Specification V4.doc

Current Version of Register Transfer Language Specifications:
Register Transfer Language SpecificationsV5.doc

Design Process Journal: DesignProcessJournal 10-31.doc

Assembler Info:
        Assembler (requires Java runtime): Assembler.class
        Assembler Source Code: Assembler.java
        Assembler Instructions: Assembler Read-Me2.txt

Mile Stone #5

Narrative and Testbenches: Narrative and Testbenches.doc

Memo for this Mile Stone: Memo for Milestone 5.doc

Design Process Journal up to Mile Stone 5: DesignProcessJournal 10-31.doc

Mile Stone #4

Drawing designs (.gif format): 16 Bit Register Without Control,One Bit Adder,One Bit ALU,16 Bit Register,Special Purpose Register File

Written descriptions and specifications: Component Specifications

Memo for Mile Stone #4: Memo for Milestone #4

Design Process Journal (up to Mile Stone 4): Design Process Journal

Revised Version of Assembly Language Specifications

Mile Stone #3

Data Path and Control Design: Data Path and Control Design.doc

Data Path Design: DataPath.GIF

Memo for Mile Stone #3: Memo for Milestone 3.doc

Design Process Journal (up to Mile Stone 3): DesignProcessJournal 10-15.doc

Mile Stone #2

Assembly Language Specifications (revised): Assembly Language Specifications V4.doc

Machine Language Specifications (revised): Machine Language Specification V4.doc

Memo for Mile Stone #2: Memo for Milestone 2.doc

Design Process Journal (since Mile Stone #1): DesignProcessJournal.doc

Mile Stone #1

Assembly Language Specifications: Assembly Language Specifications.doc

Machine Language Specifications: Machine Language Specification.doc

Memo for Mile Stone #1: Memo#1.doc

Design Process Journal: DesignProcessJournal.doc

Meeting 1-9/22/03:

Live notes from first meeting: Day1 cleaned.rtf (best when viewed with MSWordPad)

Machine Language Specifications: Assembly Language Specifications.doc

GCD Program in Assembly: AssemblyLanguageTrialProgram.doc

Final Decisions:

Addressing Modes: Addressing types.rtf (best when viewed with MSWordPad)

Final Decisions on processor overview: Day1-Final Decisions.rtf (best when viewed with MSWordPad)

Meeting 2-9/23/03:

Live notes from this meeting:Day2 cleaned.rtf (best when viewed with MSWordPad)

Machine Language Specifications: Assembly Language Specifications V2.doc

GCD Program in Assembly: AssemblyLanguageTria V2l.doc

First Draft of Memo #1: Memo #1.doc (9-23-03)

Final Decisions: Day2 decisions.rtf (best when viewed with MSWordPad)

Meeting 3-9/24/03:

Live notes from this meeting: Day 3.doc

Meeting 4-9/30/03:

Live notes from this meeting: Day 4

Meeting 5-10/2/03:

Live notes from this meeting: Day 5

Latest Version of Register Transfer Language: Register Transfer Language Specifications V2

Latest Version of Assembly Language Specifications: Assembly Language Specifications V4.doc

New compiler written by Geoffrey Ulman: Assembler

Meeting 6-10/14/03:

Live notes from this meeting: DesignProcessJournal

Updated Register Transfer Language Specifications: Register Transfer Language SpecificationsV5.doc

Meeting 7-10/15/03:

Live notes from this meeting: DesignProcessJournal

Updated Register Transfer Language Specifications: Register Transfer Language SpecificationsV5.doc

Meeting 8-10/22/03:

Live notes from this meeting: DesignProcessJournal 10-22.doc

Drawing designs (.gif format): One Bit ALU, One Bit Adder, 16-Bit Register with No Control Signal,
Diagram of ButtonEnabler in Register

Meeting 8-10/22/03:

Live notes from this meeting: Design Process Journal

Last Updated by Jeremy Fox
11/16/03, 12:02am