Team 1-1 Comp Arch Project.

Design Journal

Milestone 1

Assembly Language Spec

Machine Language Spec

Milestone 1 memo

Milestone 2

Machine Language Spec (updated)

Assembly Language Spec (updated)

English Definitions of Components

RTL Spec

Tests for Milestone 2

Milestone 2 memo

Milestone 3

Machine Language Spec (updated)

Assembly Language Spec (updated)

Control Signal Descriptions (not correct)

Control Signal Values

Datapath (visio)

Datapath (gif)

Finite State Machine (stateCad)

Milestone 4

Component specs:

            16-bit ALU (gif)

            1-bit ALU (gif)

            component spec document (updated)

             Register file (gif)

Memo

control signal descriptions (updated per grader comments)

Milestone 5

16-bit ALU (rar of xilinx stuff)

Control (rar of xilinx stuff)

Random Parts (rar of xilinx stuff)

memo is in cvs turnin