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22 September 2009
SIGNAL CHAIN BASICS (Part 9): SAR Converter Operation Explored

The Signal Chain Basics Series continues with a discussion of the successive-approximation converter (SAR) architecture

By Bill Klein, Senior Applications Engineer, Texas Instruments
Planet Analog
March 1, 2008 (12:00 PM EST)

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(Editor's Note: There are links to the previous parts of this series at the end, below the author's biography.)

Part 3 and Part 4 of this series introduced the concept of analog-to-digital conversion and listed the four major topologies. (The operation of the sigma-delta converter, the last of the four, will be examined in Part 10.)

The successive-approximation register converter (SAR converter) is a hardware realization of a binary-search tree. In concept, a logic circuit takes a guess at a digital value, stores that in a latch and applies it to a digital-to-analog converter (DAC). A comparator determines if the guess, as reported by the DAC, is high or low and then reports to the logic, to guide the next guess.

The first guess is established mid-way between zero and full scale, done by setting the most significant bit (MSB) to one. If Vin is greater than the DAC output, the bit is left on. If less than one, it is reset to zero. This binary-search tree procedure continues, on each successive clock cycle, to test the next-lower significant bit.

The D/A converter of Figure 1 is built from a resistor ladder:

Figure 1: SAR block diagram

The value of Vin must not change during the entire conversion procedure. Therefore, this circuit requires an external sample-and-hold (S/H) function. In place of the resistive-ladder DAC, most modern devices use a capacitive digital-to-analog converter (C-DAC), Figure 2, which inherently provides the S/H function, by nature of its design.

Figure 2: Three-Bit C-DAC Circuit
(Click on image to enlarge)

The operation of a C-DAC uses a charge-redistribution technique to set the test voltages for the binary search. The capacitor string is composed of a number of capacitors, equal to the number of bits of C-DAC resolution plus a dummy capacitor. The capacitor associated with the MSB is the largest. Each successive capacitor is half the size of the previous one, thereby establishing the binary sequence.

The parallel sum of the capacitors is equal to 2 N-1 C. Adding the dummy capacitor, which is equal in value to the LSB capacitor, brings the total capacitance to 2N C. Since the total capacitance is an even binary number, the repeated binary division does not leave any remainder to consider.

The following example demonstrates the conversion process as accomplished with the C-DAC version of a SAR converter:

(Click on image to enlarge)

Possible comparator results are:

At the end of this sequence, the voltage left on the COM node is negative, and of magnitude less than the value of the bit just determined.

This procedure is then repeated for the next bit, MSB-1. The process is repeated for each bit in the conversion, always leaving a voltage less than the step size for that bit.

The C-DAC has the advantage that capacitors are smaller in silicon area than resistors, so the chip cost is lower. Thus, the capacitor structure provides a built in S/H function while also reducing cost and complexity for the user. In Part 10 , we will examine the delta-sigma converter topology.

About the author

William P. (Bill) Klein is a Senior Applications Engineer with the High Performance Analog group at Texas Instruments. Bill joined TI through its acquisition of Burr-Brown in August 2000. His experience as an analog circuit designer covers over 40 years in fields ranging from mineral exploration to medical nuclear imaging. One current role Bill has is hosting the Analog e-LAB Web Cast, presenting real world solutions to real world problems in analog circuit design. In addition to a BSEE from Arizona State University and registration as a Professional Engineer in the State of Arizona, he has authored numerous magazine articles, application notes and conference papers.

Previous installments of this series:

"SIGNAL CHAIN BASIC Series (Part 8): Flash- and Pipeline-Converter Operation Explored", www.planetanalog.com/features/showArticle.jhtml;?articleID=206504089, click here
"SIGNAL CHAIN BASIC Series (Part 7): Op Amp Performance Specification--Bias Current", www.planetanalog.com/features/showArticle.jhtml;?articleID=206101908, click here
"SIGNAL CHAIN BASIC Series (Part 6): Op Amp Input Voltage Offset", www.planetanalog.com/features/showArticle.jhtml;?articleID=205901111, click here
"SIGNAL CHAIN BASICS Series (Part 5): Introduction to the Instrumentation Amplifier", www.planetanalog.com/features/showArticle.jhtml;?articleID=205208593, click here
"SIGNAL CHAIN BASICS Series (Part 4): Introduction to analog/digital converter (ADC) types", www.planetanalog.com/features/showArticle.jhtml;?articleID=204803631, click here
"SIGNAL CHAIN BASICS Series (Part 3): Analog and the digital world", www.planetanalog.com/features/showArticle.jhtml;?articleID=204400376, click here
"SIGNAL CHAIN BASICS Series (Part 2): Op Amp--Basic operations", www.planetanalog.com/features/showArticle.jhtml;?articleID=203101699, click here
"SIGNAL CHAIN BASICS: Operational Amplifier--The Basic Building Block", www.planetanalog.com/features/showArticle.jhtml;?articleID=202801320, click here

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