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22 September 2009
SIGNAL CHAIN BASICS (Part 32): Digital interfaces (con't) -- The I2C Bus

Understand the connection and format of the inter-integrated circuit bus, a basic, low-cost interconnection scheme

By Thomas Kugelstadt,
Senior Applications Engineer,
Texas Instruments
Planet Analog
August 6, 2009 (7:00 AM EST)

(Editor's note: This is the third and final part of "Basics" on Digital Interfaces; the first part was SCB #29 (single-ended versus differential interfaces); the second was SCB #31 (the SPI bus). There is a complete, linked list of all previous installments of this Signal Chain Basics series below the About the Author section at the end.)

The inter-integrated circuit (I2C) bus is a single-ended, multi-master, two-wire bus for efficient inter-IC communication in half-duplex mode. It uses open-drain technology, thus requiring the two lines, serial data (SDA) and serial clock (SCL), to be connected to VDD by resistors (Figure 1).

Figure 1: I2C bus
(Click on image to enlarge)

Pulling the line-to-ground is considered a logic zero while letting the line float is a logic one. This is used as a channel access method. Transitions of logic states must occur while SCL is low, transitions while SCL is high indicate START and STOP conditions. Typical supply voltages are 3.3 V and 5 V, although systems with higher or lower voltages are permitted.

I2C communication uses a 7-bit address space with 16 reserved addresses, so a theoretical maximum of 112 nodes can communicate on the same bus. In practice, however, the number of nodes is limited by the specified total bus capacitance of 400 pF, which restricts communication distances to a few meters. The specified signaling rates are 100 kbit/s (standard mode), 400 kbit/s (fast mode), 1 Mbit/s (fast mode plus), and 3.4 Mbit/s (high-speed mode).

The bus has two roles for nodes: master and slave. A master issues the clock and the slave addresses and also initiates and ends data transactions. A slave receives the clock and addresses and responds to requests from the master. Figure 2 shows a typical data transfer between master and slave.

Figure 2: Timing diagram of a complete data transfer
(Click on image to enlarge)

The master initiates a transaction by creating a START condition, followed by the 7-bit address of the slave with which it wishes to communicate. This is followed by a single Read/Write bit, representing whether the master wishes to write to (0), or to read from (1) the slave. The master then releases the SDA line to allow the slave to acknowledge the receipt of data.

The slave responds with an acknowledge bit (ACK) by pulling SDA low during the entire high time of the ninth clock pulse on SCL, after which the master continues in either transmit or receive mode (according to the R/W bit sent), while the slave continues in the complementary mode (receive or transmit, respectively).

The address and the 8-bit data bytes are sent most significant bit (MSB) first. The START bit is indicated by a high-to-low transition of SDA while SCL is high. The STOP condition is created by a low-to-high transition of SDA while SCL is high.

If the master writes to a slave, it repeatedly sends a byte with the slave sending an ACK bit. In this case, the master is in master-transmit mode and the slave is in slave-receive mode. If the master reads from a slave, it repeatedly receives a byte from the slave, while acknowledging (ACK) the receipt of every byte but the last one (Figure 3). In this situation the master is in master-receive mode and the slave is in slave-transmit mode.

The master ends the transmission with a STOP bit, or may send another START bit to maintain bus control for further transfers.

Figure3: Transmit/receive mode changes during a data transfer
(Click on image to enlarge)

When writing to a slave, a master mainly operates in transmit-mode and only changes to receive-mode when receiving acknowledgment from the slave.

When reading from a slave, the master starts in transmit-mode and then changes to receive-mode after sending a READ request (R/W bit = 1) to the slave. The slave continues in the complementary mode until the end of a transaction.

Note that the master ends a reading sequence by not acknowledging (NACK) the last byte received. This procedure resets the slave state machine and allows the master to send the STOP command.

This concludes our three-part series on digital interfaces (Signal Chain Basics #29, 31, and 32). The discussion on digital interfaces would be incomplete without mentioning a differential interface such as LVDS, so a discussion of this particular interface will follow later this year.

Next month, we'll talk about driving analog-to-digital converters.

About the Author

Thomas Kugelstadt is a Senior Systems Engineer at Texas Instruments, where he is responsible for defining new, high-performance analog products and developing complete system solutions that detect and condition low-level analog signals in industrial systems.
During his 20 years with TI, he has been assigned to various international application positions in Europe, Asia and the U.S. Thomas is a Graduate Engineer from the Frankfurt University of Applied Science. You can contact Thomas about this article at: [email-masked].

Previous installments of this series:

SIGNAL CHAIN BASICS (Part 31): Digital interfaces (con't) -- The SPI Bus, click here
SIGNAL CHAIN BASICS (Part 30): Protocol selection over IEEE 802.15.4 silicon, click here
SIGNAL CHAIN BASICS (Part 29): Digital interfaces - Single-ended versus differential interfaces, click here
SIGNAL CHAIN BASICS (Part 28): Building (Electrical) Bridges, click here
SIGNAL CHAIN BASICS (Part 27): Control EMI resulting from board-level clock distribution, click here
SIGNAL CHAIN BASICS (Part 26): How to close timing on High-Speed ADCs, click here
SIGNAL CHAIN BASICS (Part 25): Designing the audio-signal chain for non-audio experts, Part 1, click here
SIGNAL CHAIN BASICS (Part 24): Basic networking using the IEEE 802.15.4 PHY/MAC protocol, click here
SIGNAL CHAIN BASICS (Part 23): EIA-485: Receiver equalization boosts networking performance, click here
SIGNAL CHAIN BASICS (Part 22): Phantom microphone power--the ghost in the machine, click here
SIGNAL CHAIN BASICS (Part 21): Understand and configure analog and digital grounds, click here
SIGNAL CHAIN BASICS (Part 20): Understand the basics of op amps and speed, click here
SIGNAL CHAIN BASICS (Part 19): Exploring and understanding linear voltage regulators, click here
SIGNAL CHAIN BASICS (Part 18): The op amp as integrator, click here
SIGNAL CHAIN BASICS (Part 17): Hysteresis--Understanding more about the analog voltage comparator, click here
SIGNAL CHAIN BASICS (Part 16): Understanding the analog voltage comparator, click here
SIGNAL CHAIN BASICS (Part 15): Analog/digital converter--dynamic parameters, click here
SIGNAL CHAIN BASICS (Part 14): Analog/digital converter--static parameters, click here
SIGNAL CHAIN BASICS (Part 13): Putting the Bode plot to use, click here
SIGNAL CHAIN BASICS (Part 12): The Bode plot, an essential ac-parameter display tool, click here
SIGNAL CHAIN BASICS (Part 11): Introducing voltage- and power-conditioning circuits, click here
SIGNAL CHAIN BASICS (Part 10): Exploring the Delta-Sigma Converter, click here
SIGNAL CHAIN BASICS (Part 9): SAR Converter Operation Explored, click here
SIGNAL CHAIN BASICS (Part 8): Flash- and Pipeline-Converter Operation Explored, click here
SIGNAL CHAIN BASICS (Part 7): Op Amp Performance Specification--Bias Current, click here
SIGNAL CHAIN BASICS (Part 6): Op Amp Input Voltage Offset, click here
SIGNAL CHAIN BASICS (Part 5): Introduction to the Instrumentation Amplifier, click here
SIGNAL CHAIN BASICS (Part 4): Introduction to analog/digital converter (ADC) types, click here
SIGNAL CHAIN BASICS (Part 3): Analog and the digital world, click here
SIGNAL CHAIN BASICS (Part 2): Op Amp--Basic operations, click here
SIGNAL CHAIN BASICS: Operational Amplifier--The Basic Building Block, click here

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