// Verilog test fixture created from schematic /home/stammsl/Desktop/muxtest/mux2b4.sch - Wed Oct  9 15:47:15 2019

`timescale 1ns / 1ps

module mux2b4_mux2b4_sch_tb();

// Inputs
   reg [1:0] a;
   reg [1:0] b;
   reg [1:0] c;
   reg [1:0] d;
   reg [1:0] s;

// Output
   wire [1:0] r;

// Bidirs

// Instantiate the UUT
   v_mux2b4 UUT (
    .a(a), 
    .b(b), 
    .c(c), 
    .d(d), 
    .r(r), 
    .s(s)
   );
// Initialize Inputs
  initial begin
  
    // initialize circuits
    s = 0;
    a = 0;
    b = 0;
    c = 0;
    d = 0;
    #10;
  
    // apply stimulus
      
    // check output
    repeat (4) begin
      repeat (4) begin
       repeat (4) begin
         repeat (4) begin
          repeat (4) begin
            #1;
            case (s)
              2'b00: if (a != r)  $display("FAIL! a=%d (s = %d)", a, s);
              2'b01: if (b != r)  $display("FAIL! b=%d (s = %d)", b, s);
              2'b10: if (c != r)  $display("FAIL! c=%d (s = %d)", c, s);
              2'b11: if (d != r)  $display("FAIL! d=%d (s = %d)", d, s);
            endcase
            a = a + 1;
          end
          b = b + 1;
        end
        c = c + 1;
      end
      d = d + 1;
     end
     s = s + 1;
    end
    
  end // initial begin
endmodule