// Verilog test fixture created from schematic /home/stammsl/Desktop/muxtest/mux2b2.sch - Wed Oct  9 15:25:01 2019

`timescale 1ns / 1ps

module mux2b2_mux2b2_sch_tb();

// Inputs
   reg s;
   reg [1:0] a;
   reg [1:0] b;

// Output
   wire [1:0] r;

// Bidirs

// Instantiate the UUT
   v_mux2b2 UUT (
		.s(s), 
		.a(a), 
		.b(b), 
		.r(r)
   );
// Initialize Inputs

	initial begin
	
	  // initialize circuits
	  s = 0;
	  a = 0;
	  b = 0;
	  #10;
	
	  // apply stimulus
		  
	  // check output
	  repeat (2) begin
		  repeat (4) begin
			 repeat (4) begin
				#1;
				if (s == 0) begin
				  if (a == r)  $display("PASS! a=%d (s = %d)", a, s);
				  else         $display("FAIL! a=%d (s = %d)", a, s);
				end
				else begin
				  if (b == r)  $display("PASS! b=%d (s = %d)", b, s);
				  else         $display("FAIL! b=%d (s = %d)", b, s);
				end
				a = a + 1;
			 end
			 b = b + 1;
		  end
		  s = ~s;
	  end
	  
	end // initial begin
  
endmodule