/* Another example of a 4-bit Shift register using blocking assignments.*/

module shift_reg_rev (a,b,c,d,e,clk,reset);
output a;
input e,clk, reset;
output b,c,d;

reg a,b,c,d;

always @ (posedge clk or posedge reset)
begin
	if(reset) begin a=0;b=0;c=0;d=0; end
	else
		begin
			d=e;              //e is the input.
			c=d;              //Values change in sequence.
			b=c;              //Effectively "a" gets the value of "e"
			a=b;		  //instead of the value of "b".
		end			  //See shift_reg_nonblk.v for solution.
end
endmodule