//A 4-input, 32-bit MUX using "case" statements and "if" statements.

module mux_4_32_case_2 (mux_out,data1,data2,data3,data0,select);
output [31:0] 	mux_out;
input  [31:0] data1;
input [31:0] data2;
input [31:0] data3;
input [31:0] data0;
input  [1:0]  select;

reg 	[31:0] mux_out;  	//Target of "cyclic beavioral code" must be a register.

always @ (data1 or data2 or data3 or data0 or select) //Level sensitive sensitivity list.
						      //combinational logic.
	case(select)
		0:	begin			      //If there is more than 1 statement,
			  mux_out <= data0;           //you must enclose them with
			end			      //begin .... end
		1:	mux_out <= data1;
		2:	mux_out <= data2;
		3:	mux_out <= data3;
		default: mux_out <= 32'bx;	      //Do not use "default" for
						      //synthesis.
	endcase

/* Alternately, using "if" statements, we have

always @ (data1 or data2 or data3 or data0 or select)

	if(select == 0) mux_out = data0; 
	else if(select == 1) mux_out = data1; 
	else if(select == 2) mux_out = data2; 
	else if(select == 3) mux_out = data3; 
	else mux_out = 32'bx;  			     
*/						//x in Verilog does not mean a 						    		 	//don't care. It means "undefined".
						//A signal can have 4 values: 0,1,x 						     		//and z. "z" is a high-impedance 						     		//state.

endmodule