/*A 1-bit full adder written in behavoiral Verilog.
Uses "cyclic-beavioral" code, with blocking statements. */
*/


module fa_cyclic_behav (sum,cout,a,b,cin);

input a,b,cin;
output cout,sum;

reg cout,sum;  	//Targets of cyclic behavior statements must be "registers".

//Cyclic behavior - the always loop is  run everytime there is a change in the level(value) 
//"a", "b" or "cin". The statements within the begin ... end block are both re-evaluated //for any change in any of the inputs. However, they are evaluated in sequence and hence //the order of the statements is important.
//The evaluation of "cout" is blocked until "sum" is evaluated, hence these are called
//"blocking assignments".

always @ (a or b or cin)
begin
	 sum = a ^ b ^ cin;	   //sum and cout must be declared registers.
	 cout = (a & b) | (cin & a )| ( cin & b);	
end

endmodule