/* An asynchronous D ff i.e. the inputs set and reset are asynchronous. 
An example using both continuous assignment and cyclic behavioral code*/

module asynch_dff (q,q_bar,data,set,clk,reset);
output q,q_bar;
input data,clk, reset,set;


reg q; 			//The target in an "always @" or cyclic behavioral assignment
			//must be a register.

			//Output ports can be wires or registers.

			//Input ports can only be wires.

assign q_bar = ~q;      //This is a continuous assignment statement.
			//This cannot be placed inside a always@ block.
			//It behaves just like an always@ block, but cannot handle
			//edge-sensitive inputs.
			//Can be used for level-sensitive and combinational circuits.
			//The target of an assign statment must be a wire. 
			//By default, all signals are wires, unless otherwise defined.
			

//The sensitivity list of the always@ contains all the edge-sensitive inputs. 
//If you have a mixture of edge-sensitive and level-sensitive inputs in the sensitivity //list, the Verilog code cannot be synthesized(translated to gates for implementation)
//but can be simulated.

always @ (posedge clk or negedge reset or negedge set)
begin  				//Use "begin" and "end" if you have more than 1 statement.
	if(reset==0) 
		q <= 0 ;       // q must be defined as  a register
	else if (set == 0)     
	     	q <= 1;
	else
		q <= data;	//Since data is a synchronous input, i.e. affects the 				//output when the clock changes, it should be the last
				//clause in the sequence of conditional statements, so
				//during synthesis, it can be identified as the synchronous
				//input and will be held until the next clock transition.
							
end
endmodule