/* A shift register using blocking statements */

module shift_reg (a,b,c,d,e,clk,reset);
output a;
input e,clk, reset;
output b,c,d;

reg a,b,c,d;

always @ (posedge clk or posedge reset)
begin
	if(reset) begin a=0;b=0;c=0;d=0; end
	else
		begin			
			a=b;		//Occur sequentially from top-to-bottom
			b=c;		//See shift_reg_rev.v to see how this can
			c=d;		// be a problem.
			d=e;
		end
end
endmodule