/* 4-bit shift register, using non-blocking assignments */

module shift_reg_nonblk (a,b,c,d,e,reset,clk);
output a,b,c,d;
input e,clk, reset;


reg a,b,c,d;



always @ (posedge clk or posedge reset)  
begin
	if(reset) 
		begin
			a<=0; b<=0 ; c<= 0; d<=0;
		end

	else 
		begin
	     		d <= e;  // The "<=" non-blocking assignment is used here.
			c <= d;  //All the instructions are executed in parallel, as they
			b <= c;  // are non-blocking.
			a <= b;  //See shift_reg_rev.v and shift_reg.v for examples of
		end              //blocking assignments.
			
end
endmodule