The Verilog files should be read in the following order, to better understand the various aspects of the design.

1. four_bit_adder_struct.v - describes a 4-bit adder using structural code.
   Includes full_adder structual description that uses primitives.
2. fa_behav.v - describes a full adder using behavioral code, specifically "continuous assignement".
3. fa_adder_cyclic.v - full adder using behavioral code, specifically "cyclic assignment",
using "blocking assignments".
4. shift_reg.v - 4-bit shift register, using "cyclic assignment", with a sensitivity list
that has edge-sensitive inputs and using blocking assignments.
5. shift_reg_rev.v - Same device as above, indicates how "blocking assignments" can be mis-leading.
6. shift_reg_nonblk.v - Same device as above, using non-blocking assignments.
7. asynch_dff.v - Use of continuous assignment and cyclic assignment. Also, describes how to handle asnychronous and synchronous input.
8. mux_4_32_if_2.v - An example for  "if" statements.
9. mux_4_32_case_2.v - An example with "case" statements.

Double-clicking on the files(.v extension) causes ModelSim to try and simulate the file.
Instead, to default to Notepad or your favorite editor, right click on the file, select 
"Open With" and select your editor of choice. Check the box that says "open all files of
 the type with this application" or something to that effect.