module reg8bit(D, WE, RST, Q, CLK);
	input [7:0] D;
	input WE, RST, CLK;
	output [7:0] Q;

	reg [7:0] Q;

	always @ (posedge CLK) begin
		if(RST) begin
			Q <= 0;
		end
		else if(WE) begin
			Q <= D;
		end
	end
endmodule

module reg16bit(D, WE, RST, Q, CLK);
	input [15:0] D;
	input WE, RST, CLK;
	output [15:0] Q;

	reg [15:0] Q;

	always @ (posedge CLK) begin
		if(RST) begin
			Q <= 0;
		end
		else if(WE) begin
			Q <= D;
		end
	end
endmodule