// C:\FINAL
// Verilog Annotation Test Bench created by
// HDL Bencher 6.1i
// Fri Feb 13 12:12:24 2004

`timescale 1ns/1ns

`define RAM_A_UPPER	10
`define RAM_WIDTH	16
`define RAM_A_LOWER	0
`define RAM_C_LOWER	40
`define RAM_B_LOWER	1024
`define ADDR_SZ	3
`define RAM_C_UPPER	50
`define REG_WIDTH	16
`define RAM_A_SZ	32
`define RAM_B_UPPER	30
`define RAM_B_SZ	32

module bitand_test;
	reg [15:0] A;
	reg [15:0] B;
	wire [15:0] Q;

	bitand UUT (
		.A(A),
		.B(B),
		.Q(Q)
	);

	integer TX_FILE;
	integer TX_ERROR;

always begin // Annotate outputs process
	#50
	ANNOTATE_Q;
	#50
	 begin end //null command
end

initial
begin
	TX_ERROR=0;
	TX_FILE=$fopen("c:\\final\\bitand_test.ano");

	// --------------------
	A = 16'b0000000000000000; //0
	B = 16'b0000000000000000; //0
	// --------------------
	#100 // Time=100 ns
	A = 16'b1111111111111111; //FFFF
	// --------------------
	#100 // Time=200 ns
	B = 16'b1010101010101010; //AAAA
	// --------------------
	#100 // Time=300 ns
	A = 16'b1100110011001100; //CCCC
	// --------------------
	#100 // Time=400 ns
	A = 16'b1111111111111111; //FFFF
	B = 16'b1111111111111111; //FFFF
	// --------------------
	#200 // Time=600 ns
	// --------------------

	begin
		$display("Success! Annotation Simulation Complete.");
		$fdisplay(TX_FILE,"Total[%d]",TX_ERROR);
	end

	$fclose(TX_FILE);
	$stop;

end

task ANNOTATE_Q;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,Q,%b]",
			$time, Q);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

endmodule
