[COREGEN.VERILOG Component Instantiation.A]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="a YourInstanceName ("
text007="    .D(D),"
text008="    .Q(Q),"
text009="    .CLK(CLK));"
text010=""
text011=" "
type=template
[COREGEN.VERILOG Component Instantiation.DR]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="dr YourInstanceName ("
text007="    .D(D),"
text008="    .Q(Q),"
text009="    .CLK(CLK),"
text010="    .SSET(SSET));"
text011=""
text012=" "
type=template
[COREGEN.VERILOG Component Instantiation.Flags]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="flags YourInstanceName ("
text007="    .D(D),"
text008="    .Q(Q),"
text009="    .CLK(CLK));"
text010=""
text011=" "
type=template
[COREGEN.VERILOG Component Instantiation.IEB]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="ieb YourInstanceName ("
text007="    .D(D),"
text008="    .Q(Q),"
text009="    .CLK(CLK),"
text010="    .SSET(SSET));"
text011=""
text012=" "
type=template
[COREGEN.VERILOG Component Instantiation.ir]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="ir YourInstanceName ("
text007="    .D(D),"
text008="    .Q(Q),"
text009="    .CLK(CLK),"
text010="    .SSET(SSET));"
text011=""
text012=" "
type=template
[COREGEN.VERILOG Component Instantiation.PC]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="pc YourInstanceName ("
text007="    .D(D),"
text008="    .Q(Q),"
text009="    .CLK(CLK),"
text010="    .SSET(SSET));"
text011=""
text012=" "
type=template
[COREGEN.VERILOG Component Instantiation.Shifter]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="shifter YourInstanceName ("
text007="    .CLK(CLK),"
text008="    .SDIN(SDIN),"
text009="    .P_LOAD(P_LOAD),"
text010="    .D(D),"
text011="    .Q(Q),"
text012="    .LSB_2_MSB(LSB_2_MSB));"
text013=""
text014=" "
type=template
[COREGEN.VERILOG Component Instantiation.sp]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="sp YourInstanceName ("
text007="    .D(D),"
text008="    .Q(Q),"
text009="    .CLK(CLK),"
text010="    .SSET(SSET));"
text011=""
text012=" "
type=template
[COREGEN.VHDL Component Instantiation.A]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component a"
text005="    port ("
text006="    D: IN std_logic_VECTOR(15 downto 0);"
text007="    Q: OUT std_logic_VECTOR(15 downto 0);"
text008="    CLK: IN std_logic);"
text009="end component;"
text010=""
text011=""
text012=""
text013=" "
text014="-------------------------------------------------------------"
text015=" "
text016="-- The following code must appear in the VHDL architecture body."
text017="-- Substitute your own instance name and net names."
text018=" "
text019="your_instance_name : a"
text020="        port map ("
text021="            D => D,"
text022="            Q => Q,"
text023="            CLK => CLK);"
text024=" "
type=template
[COREGEN.VHDL Component Instantiation.DR]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component dr"
text005="    port ("
text006="    D: IN std_logic_VECTOR(15 downto 0);"
text007="    Q: OUT std_logic_VECTOR(15 downto 0);"
text008="    CLK: IN std_logic;"
text009="    SSET: IN std_logic);"
text010="end component;"
text011=""
text012=""
text013=""
text014=" "
text015="-------------------------------------------------------------"
text016=" "
text017="-- The following code must appear in the VHDL architecture body."
text018="-- Substitute your own instance name and net names."
text019=" "
text020="your_instance_name : dr"
text021="        port map ("
text022="            D => D,"
text023="            Q => Q,"
text024="            CLK => CLK,"
text025="            SSET => SSET);"
text026=" "
type=template
[COREGEN.VHDL Component Instantiation.Flags]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component flags"
text005="    port ("
text006="    D: IN std_logic_VECTOR(3 downto 0);"
text007="    Q: OUT std_logic_VECTOR(3 downto 0);"
text008="    CLK: IN std_logic);"
text009="end component;"
text010=""
text011=""
text012=""
text013=" "
text014="-------------------------------------------------------------"
text015=" "
text016="-- The following code must appear in the VHDL architecture body."
text017="-- Substitute your own instance name and net names."
text018=" "
text019="your_instance_name : flags"
text020="        port map ("
text021="            D => D,"
text022="            Q => Q,"
text023="            CLK => CLK);"
text024=" "
type=template
[COREGEN.VHDL Component Instantiation.IEB]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component ieb"
text005="    port ("
text006="    D: IN std_logic_VECTOR(0 downto 0);"
text007="    Q: OUT std_logic_VECTOR(0 downto 0);"
text008="    CLK: IN std_logic;"
text009="    SSET: IN std_logic);"
text010="end component;"
text011=""
text012=""
text013=""
text014=" "
text015="-------------------------------------------------------------"
text016=" "
text017="-- The following code must appear in the VHDL architecture body."
text018="-- Substitute your own instance name and net names."
text019=" "
text020="your_instance_name : ieb"
text021="        port map ("
text022="            D => D,"
text023="            Q => Q,"
text024="            CLK => CLK,"
text025="            SSET => SSET);"
text026=" "
type=template
[COREGEN.VHDL Component Instantiation.ir]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component ir"
text005="    port ("
text006="    D: IN std_logic_VECTOR(15 downto 0);"
text007="    Q: OUT std_logic_VECTOR(15 downto 0);"
text008="    CLK: IN std_logic;"
text009="    SSET: IN std_logic);"
text010="end component;"
text011=""
text012=""
text013=""
text014=" "
text015="-------------------------------------------------------------"
text016=" "
text017="-- The following code must appear in the VHDL architecture body."
text018="-- Substitute your own instance name and net names."
text019=" "
text020="your_instance_name : ir"
text021="        port map ("
text022="            D => D,"
text023="            Q => Q,"
text024="            CLK => CLK,"
text025="            SSET => SSET);"
text026=" "
type=template
[COREGEN.VHDL Component Instantiation.PC]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component pc"
text005="    port ("
text006="    D: IN std_logic_VECTOR(15 downto 0);"
text007="    Q: OUT std_logic_VECTOR(15 downto 0);"
text008="    CLK: IN std_logic;"
text009="    SSET: IN std_logic);"
text010="end component;"
text011=""
text012=""
text013=""
text014=" "
text015="-------------------------------------------------------------"
text016=" "
text017="-- The following code must appear in the VHDL architecture body."
text018="-- Substitute your own instance name and net names."
text019=" "
text020="your_instance_name : pc"
text021="        port map ("
text022="            D => D,"
text023="            Q => Q,"
text024="            CLK => CLK,"
text025="            SSET => SSET);"
text026=" "
type=template
[COREGEN.VHDL Component Instantiation.Shifter]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component shifter"
text005="    port ("
text006="    CLK: IN std_logic;"
text007="    SDIN: IN std_logic;"
text008="    P_LOAD: IN std_logic;"
text009="    D: IN std_logic_VECTOR(15 downto 0);"
text010="    Q: OUT std_logic_VECTOR(15 downto 0);"
text011="    LSB_2_MSB: IN std_logic);"
text012="end component;"
text013=""
text014=""
text015=""
text016=" "
text017="-------------------------------------------------------------"
text018=" "
text019="-- The following code must appear in the VHDL architecture body."
text020="-- Substitute your own instance name and net names."
text021=" "
text022="your_instance_name : shifter"
text023="        port map ("
text024="            CLK => CLK,"
text025="            SDIN => SDIN,"
text026="            P_LOAD => P_LOAD,"
text027="            D => D,"
text028="            Q => Q,"
text029="            LSB_2_MSB => LSB_2_MSB);"
text030=" "
type=template
[COREGEN.VHDL Component Instantiation.sp]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component sp"
text005="    port ("
text006="    D: IN std_logic_VECTOR(15 downto 0);"
text007="    Q: OUT std_logic_VECTOR(15 downto 0);"
text008="    CLK: IN std_logic;"
text009="    SSET: IN std_logic);"
text010="end component;"
text011=""
text012=""
text013=""
text014=" "
text015="-------------------------------------------------------------"
text016=" "
text017="-- The following code must appear in the VHDL architecture body."
text018="-- Substitute your own instance name and net names."
text019=" "
text020="your_instance_name : sp"
text021="        port map ("
text022="            D => D,"
text023="            Q => Q,"
text024="            CLK => CLK,"
text025="            SSET => SSET);"
text026=" "
type=template
