// C:\TEAM2-5
// Verilog Annotation Test Bench created by
// HDL Bencher 6.1i
// Sat Feb 14 20:26:36 2004

`timescale 1ns/1ns

`define RAM_WIDTH	16
`define RAM_A_LOWER	0
`define RAM_C_LOWER	40
`define RAM_B_LOWER	1024
`define ADDR_SZ	3
`define RAM_C_UPPER	50
`define REG_WIDTH	16
`define RAM_A_SZ	32
`define RAM_B_UPPER	30
`define RAM_A_UPPER	10
`define RAM_B_SZ	32

module IR_test;
	reg [15:0] D;
	reg WE;
	reg CLK;
	wire [5:0] Q1510;
	wire [1:0] Q98;
	wire [1:0] Q76;
	wire [7:0] Q70;

	IR UUT (
		.D(D),
		.WE(WE),
		.CLK(CLK),
		.Q1510(Q1510),
		.Q98(Q98),
		.Q76(Q76),
		.Q70(Q70)
	);

	integer TX_FILE;
	integer TX_ERROR;

always
begin 			//clock process
	CLK = 1'b0;
	#10
	CLK = 1'b1;
	#10
	ANNOTATE_Q1510;
	ANNOTATE_Q98;
	ANNOTATE_Q76;
	ANNOTATE_Q70;
	#40
	CLK = 1'b0;
	#40
	CLK = 1'b0;
end

initial
begin
	TX_ERROR=0;
	TX_FILE=$fopen("c:\\team2-5\\ir_test.ano");

	// --------------------
	D = 16'b1010101100101010; //AB2A
	WE = 1'b0;
	// --------------------
	#200 // Time=200 ns
	WE = 1'b1;
	// --------------------
	#100 // Time=300 ns
	WE = 1'b0;
	// --------------------
	#110 // Time=410 ns
	// --------------------

	begin
		$display("Success! Annotation Simulation Complete.");
		$fdisplay(TX_FILE,"Total[%d]",TX_ERROR);
	end

	$fclose(TX_FILE);
	$stop;

end

task ANNOTATE_Q1510;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,Q1510,%b]",
			$time, Q1510);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_Q98;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,Q98,%b]",
			$time, Q98);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_Q76;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,Q76,%b]",
			$time, Q76);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_Q70;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,Q70,%b]",
			$time, Q70);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

endmodule
