(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2004 2 12 23 54 55)
   (author "Xilinx, Inc.")
   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 6.1.03i; Cores Update # 1"))))
   (comment "                                                                                
      This file is owned and controlled by Xilinx and must be used              
      solely for design, simulation, implementation and creation of             
      design files limited to Xilinx devices or technologies. Use               
      with non-Xilinx devices or technologies is expressly prohibited           
      and immediately terminates your license.                                  
                                                                                
      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'             
      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                   
      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION           
      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION               
      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                 
      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                   
      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE          
      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                  
      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                   
      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR            
      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF           
      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS           
      FOR A PARTICULAR PURPOSE.                                                 
                                                                                
      Xilinx products are not intended for use in life support                  
      appliances, devices, or systems. Use in such applications are             
      expressly prohibited.                                                     
                                                                                
      (c) Copyright 1995-2003 Xilinx, Inc.                                      
      All rights reserved.                                                      
                                                                                
   ")
   (comment "Core parameters: ")
       (comment "c_width = 8 ")
       (comment "c_has_sinit = false ")
       (comment "c_sinit_val = 00000000 ")
       (comment "c_has_ce = false ")
       (comment "c_family = virtex ")
       (comment "c_ainit_val = 11111111 ")
       (comment "c_sync_enable = 0 ")
       (comment "c_has_aset = false ")
       (comment "InstanceName = ds ")
       (comment "c_enable_rlocs = true ")
       (comment "c_has_aclr = false ")
       (comment "c_has_sset = true ")
       (comment "c_sync_priority = 1 ")
       (comment "c_has_ainit = false ")
       (comment "c_has_sclr = false ")
   (external xilinxun (edifLevel 0)
      (technology (numberDefinition))
       (cell VCC (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port P (direction OUTPUT))
               )
           )
       )
       (cell GND (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port G (direction OUTPUT))
               )
           )
       )
       (cell FDSE (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port C (direction INPUT))
                   (port CE (direction INPUT))
                   (port S (direction INPUT))
                   (port Q (direction OUTPUT))
               )
           )
       )
   )
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell ds
 (cellType GENERIC) (view view_1 (viewType NETLIST)
  (interface
   (port ( array ( rename D "D<7:0>") 8 ) (direction INPUT))
   (port ( rename CLK "CLK") (direction INPUT))
   (port ( rename SSET "SSET") (direction INPUT))
   (port ( array ( rename Q "Q<7:0>") 8 ) (direction OUTPUT))
   )
  (contents
   (instance VCC (viewRef view_1 (cellRef VCC  (libraryRef xilinxun))))
   (instance GND (viewRef view_1 (cellRef GND  (libraryRef xilinxun))))
   (instance BU3
      (viewRef view_1 (cellRef FDSE (libraryRef xilinxun)))
      (property RLOC (string "r3c0.S1"))
   )
   (instance BU5
      (viewRef view_1 (cellRef FDSE (libraryRef xilinxun)))
      (property RLOC (string "r3c0.S1"))
   )
   (instance BU7
      (viewRef view_1 (cellRef FDSE (libraryRef xilinxun)))
      (property RLOC (string "r2c0.S1"))
   )
   (instance BU9
      (viewRef view_1 (cellRef FDSE (libraryRef xilinxun)))
      (property RLOC (string "r2c0.S1"))
   )
   (instance BU11
      (viewRef view_1 (cellRef FDSE (libraryRef xilinxun)))
      (property RLOC (string "r1c0.S1"))
   )
   (instance BU13
      (viewRef view_1 (cellRef FDSE (libraryRef xilinxun)))
      (property RLOC (string "r1c0.S1"))
   )
   (instance BU15
      (viewRef view_1 (cellRef FDSE (libraryRef xilinxun)))
      (property RLOC (string "r0c0.S1"))
   )
   (instance BU17
      (viewRef view_1 (cellRef FDSE (libraryRef xilinxun)))
      (property RLOC (string "r0c0.S1"))
   )
   (net N1
    (joined
      (portRef P (instanceRef VCC))
      (portRef CE (instanceRef BU3))
      (portRef CE (instanceRef BU5))
      (portRef CE (instanceRef BU7))
      (portRef CE (instanceRef BU9))
      (portRef CE (instanceRef BU11))
      (portRef CE (instanceRef BU13))
      (portRef CE (instanceRef BU15))
      (portRef CE (instanceRef BU17))
    )
   )
   (net (rename N18 "D<0>")
    (joined
      (portRef (member D 7))
      (portRef D (instanceRef BU3))
    )
   )
   (net (rename N19 "D<1>")
    (joined
      (portRef (member D 6))
      (portRef D (instanceRef BU5))
    )
   )
   (net (rename N20 "D<2>")
    (joined
      (portRef (member D 5))
      (portRef D (instanceRef BU7))
    )
   )
   (net (rename N21 "D<3>")
    (joined
      (portRef (member D 4))
      (portRef D (instanceRef BU9))
    )
   )
   (net (rename N22 "D<4>")
    (joined
      (portRef (member D 3))
      (portRef D (instanceRef BU11))
    )
   )
   (net (rename N23 "D<5>")
    (joined
      (portRef (member D 2))
      (portRef D (instanceRef BU13))
    )
   )
   (net (rename N24 "D<6>")
    (joined
      (portRef (member D 1))
      (portRef D (instanceRef BU15))
    )
   )
   (net (rename N25 "D<7>")
    (joined
      (portRef (member D 0))
      (portRef D (instanceRef BU17))
    )
   )
   (net (rename N26 "Q<0>")
    (joined
      (portRef (member Q 7))
      (portRef Q (instanceRef BU3))
    )
   )
   (net (rename N27 "Q<1>")
    (joined
      (portRef (member Q 6))
      (portRef Q (instanceRef BU5))
    )
   )
   (net (rename N28 "Q<2>")
    (joined
      (portRef (member Q 5))
      (portRef Q (instanceRef BU7))
    )
   )
   (net (rename N29 "Q<3>")
    (joined
      (portRef (member Q 4))
      (portRef Q (instanceRef BU9))
    )
   )
   (net (rename N30 "Q<4>")
    (joined
      (portRef (member Q 3))
      (portRef Q (instanceRef BU11))
    )
   )
   (net (rename N31 "Q<5>")
    (joined
      (portRef (member Q 2))
      (portRef Q (instanceRef BU13))
    )
   )
   (net (rename N32 "Q<6>")
    (joined
      (portRef (member Q 1))
      (portRef Q (instanceRef BU15))
    )
   )
   (net (rename N33 "Q<7>")
    (joined
      (portRef (member Q 0))
      (portRef Q (instanceRef BU17))
    )
   )
   (net (rename N34 "CLK")
    (joined
      (portRef CLK)
      (portRef C (instanceRef BU3))
      (portRef C (instanceRef BU5))
      (portRef C (instanceRef BU7))
      (portRef C (instanceRef BU9))
      (portRef C (instanceRef BU11))
      (portRef C (instanceRef BU13))
      (portRef C (instanceRef BU15))
      (portRef C (instanceRef BU17))
    )
   )
   (net (rename N35 "SSET")
    (joined
      (portRef SSET)
      (portRef S (instanceRef BU3))
      (portRef S (instanceRef BU5))
      (portRef S (instanceRef BU7))
      (portRef S (instanceRef BU9))
      (portRef S (instanceRef BU11))
      (portRef S (instanceRef BU13))
      (portRef S (instanceRef BU15))
      (portRef S (instanceRef BU17))
    )
   )
))))
(design ds (cellRef ds (libraryRef test_lib))
  (property X_CORE_INFO (string "C_REG_FD_V6_0, Coregen 6.1.03i_ip1"))
  (property PART (string "XCV100BG256") (owner "Xilinx")))
)
