module IntFile(
   ReadIntAddr,
   WriteIntAddr,
   WriteData,
   IntWrite,
   ReadData,               
   CLK);

// Definitions

parameter NUM_REGS = 4;
`define ADDR_SZ 2
`define REG_WIDTH 16

// Inputs

input [`ADDR_SZ-1:0] ReadIntAddr;
input [`ADDR_SZ-1:0] WriteIntAddr;
input [`REG_WIDTH-1:0] WriteData;
input IntWrite;
input CLK;

// Outputs

output [`REG_WIDTH-1:0] ReadData;

// Signals

wire [`REG_WIDTH-1:0] ReadData;

// The registers

reg [`REG_WIDTH-1:0] Reg [NUM_REGS-1:0];

assign ReadData = Reg[ ReadIntAddr ];

// Operation

always @ ( posedge CLK ) begin
   if ( IntWrite )
      Reg[ WriteIntAddr ] <= WriteData;
end

endmodule
