module immtoflag(Q, D);

	input [7:0] Q;
	output [3:0] D;

	wire [3:0] D;

	assign D = Q[3:0];
endmodule

module regtoflag(Q, D);

	input [15:0] Q;
	output [3:0] D;

	wire [3:0] D;

	assign D = Q[3:0];
endmodule

module flagtoreg(Q, D);

	input [3:0] Q;
	output [15:0] D;

	wire [15:0] D;

	assign D = Q;
endmodule
