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--     design files limited to Xilinx devices or technologies. Use            --
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-- You must compile the wrapper file ir.vhd when simulating
-- the core, ir. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Guide".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

Library XilinxCoreLib;
ENTITY ir IS
	port (
	D: IN std_logic_VECTOR(15 downto 0);
	Q: OUT std_logic_VECTOR(15 downto 0);
	CLK: IN std_logic;
	SSET: IN std_logic);
END ir;

ARCHITECTURE ir_a OF ir IS

component wrapped_ir
	port (
	D: IN std_logic_VECTOR(15 downto 0);
	Q: OUT std_logic_VECTOR(15 downto 0);
	CLK: IN std_logic;
	SSET: IN std_logic);
end component;

-- Configuration specification 
	for all : wrapped_ir use entity XilinxCoreLib.C_REG_FD_V6_0(behavioral)
		generic map(
			c_width => 16,
			c_has_sinit => 0,
			c_has_ce => 0,
			c_sinit_val => "0000000000000000",
			c_ainit_val => "1111111111111111",
			c_sync_enable => 0,
			c_has_aset => 0,
			c_enable_rlocs => 1,
			c_has_aclr => 0,
			c_has_sset => 1,
			c_sync_priority => 1,
			c_has_ainit => 0,
			c_has_sclr => 0);
BEGIN

U0 : wrapped_ir
		port map (
			D => D,
			Q => Q,
			CLK => CLK,
			SSET => SSET);
END ir_a;

-- synopsys translate_on

