//  C:\TEAM2-5\.\THEPROJECT\CONTROL.v
//  Verilog created by Xilinx's StateCAD 6.1i
//  Wed Feb 18 10:40:08 2004

//  This Verilog code (for use with Xilinx XST) was generated using: 
//  binary encoded state assignment with structured code format.
//  Minimization is enabled,  implied else is enabled, 
//  and outputs are speed optimized.

`timescale 1s/1s

module shell_control(CLK,Cond,IRQ,OP0,OP1,OP2,OP3,OP4,OP5,RESET,ALUOp0,ALUOp1
	,ALUOp2,ALUSrcA0,ALUSrcA1,ALUSrcB0,ALUSrcB1,ComboMux,DRWrite,DSSel,DSWrite,
	FlagsSel0,FlagsSel1,FlagsWrite,IEBData,IEBWrite,IFetch,IntWrite,IRWrite,
	MemWrite,NegCond,PCSel0,PCSel1,PCSel2,PCWrite,PCWriteCond,RegSel0,RegSel1,
	RegSel2,RegSel3,RegWrite,SelIntAddr0,SelIntAddr1,SelIntData,SelMemAddr0,
	SelMemAddr1,SelMemAddr2,SelMemData0,SelMemData1,SPSel,SPWrite,SPWriteCond);

	input CLK;
	input Cond,IRQ,OP0,OP1,OP2,OP3,OP4,OP5,RESET;
	output ALUOp0,ALUOp1,ALUOp2,ALUSrcA0,ALUSrcA1,ALUSrcB0,ALUSrcB1,ComboMux,
		DRWrite,DSSel,DSWrite,FlagsSel0,FlagsSel1,FlagsWrite,IEBData,IEBWrite,IFetch,
		IntWrite,IRWrite,MemWrite,NegCond,PCSel0,PCSel1,PCSel2,PCWrite,PCWriteCond,
		RegSel0,RegSel1,RegSel2,RegSel3,RegWrite,SelIntAddr0,SelIntAddr1,SelIntData,
		SelMemAddr0,SelMemAddr1,SelMemAddr2,SelMemData0,SelMemData1,SPSel,SPWrite,
		SPWriteCond;

	reg [2:0] ALUOp;
	reg [1:0] ALUSrcA;
	reg [1:0] ALUSrcB;
	reg [1:0] FlagsSel;
	reg [2:0] PCSel;
	reg [3:0] RegSel;
	reg [1:0] SelIntAddr;
	reg [2:0] SelMemAddr;
	reg [1:0] SelMemData;
	reg ALUOp0,next_ALUOp0,ALUOp1,next_ALUOp1,ALUOp2,next_ALUOp2,ALUSrcA0,
		next_ALUSrcA0,ALUSrcA1,next_ALUSrcA1,ALUSrcB0,next_ALUSrcB0,ALUSrcB1,
		next_ALUSrcB1,ComboMux,next_ComboMux,DRWrite,next_DRWrite,DSSel,next_DSSel,
		DSWrite,next_DSWrite,FlagsSel0,next_FlagsSel0,FlagsSel1,next_FlagsSel1,
		FlagsWrite,next_FlagsWrite,IEBData,next_IEBData,IEBWrite,next_IEBWrite,IFetch
		,next_IFetch,IntWrite,next_IntWrite,IRWrite,next_IRWrite,MemWrite,
		next_MemWrite,NegCond,next_NegCond,PCSel0,next_PCSel0,PCSel1,next_PCSel1,
		PCSel2,next_PCSel2,PCWrite,next_PCWrite,PCWriteCond,next_PCWriteCond,RegSel0,
		next_RegSel0,RegSel1,next_RegSel1,RegSel2,next_RegSel2,RegSel3,next_RegSel3,
		RegWrite,next_RegWrite,SelIntAddr0,next_SelIntAddr0,SelIntAddr1,
		next_SelIntAddr1,SelIntData,next_SelIntData,SelMemAddr0,next_SelMemAddr0,
		SelMemAddr1,next_SelMemAddr1,SelMemAddr2,next_SelMemAddr2,SelMemData0,
		next_SelMemData0,SelMemData1,next_SelMemData1,SPSel,next_SPSel,SPWrite,
		next_SPWrite,SPWriteCond,next_SPWriteCond;
	reg [5:0] sreg;
	reg [5:0] next_sreg;

	`define ADD 6'b000000
	`define ADDI 6'b000001
	`define CALLA 6'b000010
	`define CALLC 6'b000011
	`define CALLNC 6'b000100
	`define CALLR 6'b000101
	`define CP 6'b000110
	`define CPI 6'b000111
	`define Decode 6'b001000
	`define DI 6'b001001
	`define EI 6'b001010
	`define Fetch 6'b001011
	`define GETI 6'b001100
	`define intAND 6'b001101
	`define intANDI 6'b001110
	`define Interrupt_PC 6'b001111
	`define Interrupt_Stack 6'b010000
	`define intOR 6'b010001
	`define intORI 6'b010010
	`define intSLL 6'b010011
	`define intSLLI 6'b010100
	`define intSLR 6'b010101
	`define intSLRI 6'b010110
	`define JPA 6'b010111
	`define JPC 6'b011000
	`define JPNC 6'b011001
	`define JPR 6'b011010
	`define LD 6'b011011
	`define LDDR 6'b011100
	`define LDDS 6'b011101
	`define LDF 6'b011110
	`define LDIL 6'b011111
	`define LDIU 6'b100000
	`define LDR 6'b100001
	`define LDRI 6'b100010
	`define LDSP 6'b100011
	`define NEG 6'b100100
	`define POP 6'b100101
	`define PUSH 6'b100110
	`define RESET1 6'b100111
	`define RESET2 6'b101000
	`define RETA 6'b101001
	`define SETI 6'b101010
	`define SETIA 6'b101011
	`define SPMinus2 6'b101100
	`define SPPlus2 6'b101101
	`define SPPlus2_C 6'b101110
	`define SPPlus2_NC 6'b101111
	`define ST 6'b110000
	`define STDR 6'b110001
	`define STDS 6'b110010
	`define STDSI 6'b110011
	`define STF 6'b110100
	`define STFI 6'b110101
	`define STRI 6'b110110
	`define STSP 6'b110111
	`define SUB 6'b111000
	`define SUBI 6'b111001
	`define WriteBack_Comp 6'b111010
	`define WriteBack_Mem 6'b111011
	`define WriteBack_Sum 6'b111100


	always @(posedge CLK)
	begin
		sreg = next_sreg;
		ComboMux = next_ComboMux;
		DRWrite = next_DRWrite;
		DSSel = next_DSSel;
		DSWrite = next_DSWrite;
		FlagsWrite = next_FlagsWrite;
		IEBData = next_IEBData;
		IEBWrite = next_IEBWrite;
		IFetch = next_IFetch;
		IntWrite = next_IntWrite;
		IRWrite = next_IRWrite;
		MemWrite = next_MemWrite;
		NegCond = next_NegCond;
		PCWrite = next_PCWrite;
		PCWriteCond = next_PCWriteCond;
		RegWrite = next_RegWrite;
		SelIntData = next_SelIntData;
		SPSel = next_SPSel;
		SPWrite = next_SPWrite;
		SPWriteCond = next_SPWriteCond;
		ALUOp2 = next_ALUOp2;
		ALUOp1 = next_ALUOp1;
		ALUOp0 = next_ALUOp0;
		ALUSrcA1 = next_ALUSrcA1;
		ALUSrcA0 = next_ALUSrcA0;
		ALUSrcB1 = next_ALUSrcB1;
		ALUSrcB0 = next_ALUSrcB0;
		FlagsSel1 = next_FlagsSel1;
		FlagsSel0 = next_FlagsSel0;
		PCSel2 = next_PCSel2;
		PCSel1 = next_PCSel1;
		PCSel0 = next_PCSel0;
		RegSel3 = next_RegSel3;
		RegSel2 = next_RegSel2;
		RegSel1 = next_RegSel1;
		RegSel0 = next_RegSel0;
		SelIntAddr1 = next_SelIntAddr1;
		SelIntAddr0 = next_SelIntAddr0;
		SelMemAddr2 = next_SelMemAddr2;
		SelMemAddr1 = next_SelMemAddr1;
		SelMemAddr0 = next_SelMemAddr0;
		SelMemData1 = next_SelMemData1;
		SelMemData0 = next_SelMemData0;
	end

	always @ (sreg or Cond or IRQ or OP0 or OP1 or OP2 or OP3 or OP4 or OP5 or 
		RESET or ALUOp or ALUSrcA or ALUSrcB or FlagsSel or PCSel or RegSel or 
		SelIntAddr or SelMemAddr or SelMemData)
	begin
		next_ALUOp0 = 0; next_ALUOp1 = 0; next_ALUOp2 = 0; next_ALUSrcA0 = 0; 
			next_ALUSrcA1 = 0; next_ALUSrcB0 = 0; next_ALUSrcB1 = 0; next_ComboMux = 0; 
			next_DRWrite = 0; next_DSSel = 0; next_DSWrite = 0; next_FlagsSel0 = 0; 
			next_FlagsSel1 = 0; next_FlagsWrite = 0; next_IEBData = 0; next_IEBWrite = 0;
			 next_IFetch = 0; next_IntWrite = 0; next_IRWrite = 0; next_MemWrite = 0; 
			next_NegCond = 0; next_PCSel0 = 0; next_PCSel1 = 0; next_PCSel2 = 0; 
			next_PCWrite = 0; next_PCWriteCond = 0; next_RegSel0 = 0; next_RegSel1 = 0; 
			next_RegSel2 = 0; next_RegSel3 = 0; next_RegWrite = 0; next_SelIntAddr0 = 0; 
			next_SelIntAddr1 = 0; next_SelIntData = 0; next_SelMemAddr0 = 0; 
			next_SelMemAddr1 = 0; next_SelMemAddr2 = 0; next_SelMemData0 = 0; 
			next_SelMemData1 = 0; next_SPSel = 0; next_SPWrite = 0; next_SPWriteCond = 0;
			 
		ALUOp=3'h0; ALUSrcA=2'h0; ALUSrcB=2'h0; FlagsSel=2'h0; PCSel=3'h0; 
			RegSel=4'h0; SelIntAddr=2'h0; SelMemAddr=3'h0; SelMemData=2'h0; 

		next_sreg=`ADD;

		if ( RESET ) begin
			next_sreg=`RESET1;
			next_SPWriteCond=0;
			next_SPWrite=0;
			next_SPSel=0;
			next_SelIntData=0;
			next_RegWrite=0;
			next_PCWriteCond=0;
			next_PCWrite=0;
			next_NegCond=0;
			next_MemWrite=0;
			next_IRWrite=0;
			next_IntWrite=0;
			next_IFetch=0;
			next_IEBWrite=0;
			next_IEBData=0;
			next_FlagsWrite=0;
			next_DSWrite=0;
			next_DSSel=0;
			next_DRWrite=0;
			next_ComboMux=0;
			ALUOp= 'h0;
			ALUSrcA= 'h0;
			ALUSrcB= 'h0;
			FlagsSel= 'h0;
			PCSel= 'h0;
			RegSel= 'h0;
			SelIntAddr= 'h0;
			SelMemAddr= 'h0;
			SelMemData= 'h0;
		end else begin
			case (sreg)
				`ADD : begin
					next_sreg=`WriteBack_Sum;
					next_SPWriteCond=0;
					next_SPWrite=0;
					next_SPSel=0;
					next_SelIntData=0;
					next_PCWriteCond=0;
					next_PCWrite=0;
					next_NegCond=0;
					next_MemWrite=0;
					next_IRWrite=0;
					next_IntWrite=0;
					next_IFetch=0;
					next_IEBWrite=0;
					next_IEBData=0;
					next_FlagsWrite=0;
					next_DSWrite=0;
					next_DSSel=0;
					next_DRWrite=0;
					next_ComboMux=0;
					next_RegWrite=1;
					ALUOp= 'h0;
					ALUSrcA= 'h0;
					ALUSrcB= 'h0;
					FlagsSel= 'h0;
					PCSel= 'h0;
					SelIntAddr= 'h0;
					SelMemAddr= 'h0;
					SelMemData= 'h0;
					RegSel= 'h5;
				end
				`ADDI : begin
					next_sreg=`WriteBack_Sum;
					next_SPWriteCond=0;
					next_SPWrite=0;
					next_SPSel=0;
					next_SelIntData=0;
					next_PCWriteCond=0;
					next_PCWrite=0;
					next_NegCond=0;
					next_MemWrite=0;
					next_IRWrite=0;
					next_IntWrite=0;
					next_IFetch=0;
					next_IEBWrite=0;
					next_IEBData=0;
					next_FlagsWrite=0;
					next_DSWrite=0;
					next_DSSel=0;
					next_DRWrite=0;
					next_ComboMux=0;
					next_RegWrite=1;
					ALUOp= 'h0;
					ALUSrcA= 'h0;
					ALUSrcB= 'h0;
					FlagsSel= 'h0;
					PCSel= 'h0;
					SelIntAddr= 'h0;
					SelMemAddr= 'h0;
					SelMemData= 'h0;
					RegSel= 'h5;
				end
				`CALLA : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`CALLC : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`CALLNC : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`CALLR : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`CP : begin
					next_sreg=`WriteBack_Comp;
					next_SPWriteCond=0;
					next_SPWrite=0;
					next_SPSel=0;
					next_SelIntData=0;
					next_RegWrite=0;
					next_PCWriteCond=0;
					next_PCWrite=0;
					next_NegCond=0;
					next_MemWrite=0;
					next_IRWrite=0;
					next_IntWrite=0;
					next_IFetch=0;
					next_IEBWrite=0;
					next_IEBData=0;
					next_DSWrite=0;
					next_DSSel=0;
					next_DRWrite=0;
					next_ComboMux=0;
					next_FlagsWrite=1;
					ALUOp= 'h0;
					ALUSrcA= 'h0;
					ALUSrcB= 'h0;
					PCSel= 'h0;
					RegSel= 'h0;
					SelIntAddr= 'h0;
					SelMemAddr= 'h0;
					SelMemData= 'h0;
					FlagsSel= 'h2;
				end
				`CPI : begin
					next_sreg=`WriteBack_Comp;
					next_SPWriteCond=0;
					next_SPWrite=0;
					next_SPSel=0;
					next_SelIntData=0;
					next_RegWrite=0;
					next_PCWriteCond=0;
					next_PCWrite=0;
					next_NegCond=0;
					next_MemWrite=0;
					next_IRWrite=0;
					next_IntWrite=0;
					next_IFetch=0;
					next_IEBWrite=0;
					next_IEBData=0;
					next_DSWrite=0;
					next_DSSel=0;
					next_DRWrite=0;
					next_ComboMux=0;
					next_FlagsWrite=1;
					ALUOp= 'h0;
					ALUSrcA= 'h0;
					ALUSrcB= 'h0;
					PCSel= 'h0;
					RegSel= 'h0;
					SelIntAddr= 'h0;
					SelMemAddr= 'h0;
					SelMemData= 'h0;
					FlagsSel= 'h2;
				end
				`Decode : begin
					if ( ~OP0 & OP1 & OP2 & ~OP3 & OP4 & ~OP5 ) begin
						next_sreg=`SPPlus2_NC;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						next_SPWriteCond=1;
						next_NegCond=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						ALUOp= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					if ( ~OP0 & OP1 & ~OP2 & OP3 & OP4 & OP5 ) begin
						next_sreg=`CALLNC;
						next_SPWriteCond=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWrite=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						next_SPWrite=1;
						next_PCWriteCond=1;
						next_NegCond=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					if ( ~OP0 & OP1 & ~OP2 & ~OP3 & OP4 & OP5 ) begin
						next_sreg=`JPNC;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWrite=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_PCWriteCond=1;
						next_NegCond=1;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h2;
					end
					if ( OP0 & ~OP1 & ~OP2 & OP3 & OP4 & OP5 ) begin
						next_sreg=`CP;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						ALUOp= 'h0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						ALUSrcB= 'h1;
						ALUSrcA= 'h2;
					end
					if ( OP0 & OP1 & OP2 & OP3 & ~OP4 & ~OP5 ) begin
						next_sreg=`CPI;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						ALUOp= 'h0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						ALUSrcB= 'h2;
						ALUSrcA= 'h2;
					end
					if ( OP0 & OP1 & OP2 & OP3 & ~OP4 & OP5 ) begin
						next_sreg=`SETIA;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IntWrite=1;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h0;
					end
					if ( OP0 & ~OP1 & OP2 & ~OP3 & ~OP4 & ~OP5 ) begin
						next_sreg=`SETI;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SelIntData=1;
						next_IntWrite=1;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h0;
					end
					if ( OP0 & ~OP1 & OP2 & ~OP3 & ~OP4 & OP5 ) begin
						next_sreg=`GETI;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_RegWrite=1;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						RegSel= 'ha;
						SelIntAddr= 'h1;
					end
					if ( ~OP0 & OP1 & ~OP2 & OP3 & ~OP4 & ~OP5 ) begin
						next_sreg=`CALLR;
						next_SPWriteCond=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						next_SPWrite=1;
						next_PCWrite=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h3;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					if ( ~OP0 & OP1 & ~OP2 & OP3 & ~OP4 & OP5 ) begin
						next_sreg=`CALLA;
						next_SPWriteCond=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						next_SPWrite=1;
						next_PCWrite=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					if ( ~OP0 & OP1 & ~OP2 & OP3 & OP4 & ~OP5 ) begin
						next_sreg=`CALLC;
						next_SPWriteCond=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						next_SPWrite=1;
						next_PCWriteCond=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					if ( ~OP0 & OP1 & ~OP2 & ~OP3 & ~OP4 & ~OP5 ) begin
						next_sreg=`JPR;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_PCWrite=1;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h1;
					end
					if ( ~OP0 & OP1 & ~OP2 & ~OP3 & ~OP4 & OP5 ) begin
						next_sreg=`JPA;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_PCWrite=1;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h2;
					end
					if ( ~OP0 & OP1 & ~OP2 & ~OP3 & OP4 & ~OP5 ) begin
						next_sreg=`JPC;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_PCWriteCond=1;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h2;
					end
					if ( ~OP0 & ~OP1 & OP2 & ~OP3 & OP4 & OP5 ) begin
						next_sreg=`PUSH;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_MemWrite=1;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h2;
						SelMemAddr= 'h1;
					end
					if ( OP0 & OP1 & ~OP2 & OP3 & ~OP4 & OP5 ) begin
						next_sreg=`LDIL;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=1;
						next_RegWrite=1;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						RegSel= 'h7;
					end
					if ( OP0 & OP1 & ~OP2 & OP3 & ~OP4 & ~OP5 ) begin
						next_sreg=`LDIU;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_RegWrite=1;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						RegSel= 'h7;
					end
					if ( OP0 & ~OP1 & ~OP2 & ~OP3 & OP4 & ~OP5 ) begin
						next_sreg=`LDR;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_RegWrite=1;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						RegSel= 'h6;
					end
					if ( OP0 & OP1 & OP2 & ~OP3 & OP4 & OP5 ) begin
						next_sreg=`STRI;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_MemWrite=1;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h4;
						SelMemData= 'h2;
					end
					if ( ~OP0 & ~OP1 & OP2 & ~OP3 & ~OP4 & ~OP5 ) begin
						next_sreg=`LDDR;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_RegWrite=1;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						RegSel= 'h3;
					end
					if ( ~OP0 & ~OP1 & ~OP2 & OP3 & OP4 & OP5 ) begin
						next_sreg=`STDR;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_ComboMux=0;
						next_DRWrite=1;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
					end
					if ( ~OP0 & ~OP1 & OP2 & ~OP3 & OP4 & ~OP5 ) begin
						next_sreg=`LDF;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_RegWrite=1;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						RegSel= 'h2;
					end
					if ( ~OP0 & ~OP1 & OP2 & ~OP3 & ~OP4 & OP5 ) begin
						next_sreg=`STF;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_FlagsWrite=1;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						FlagsSel= 'h1;
					end
					if ( OP0 & OP1 & ~OP2 & ~OP3 & ~OP4 & OP5 ) begin
						next_sreg=`STFI;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_FlagsWrite=1;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						FlagsSel= 'h0;
					end
					if ( ~OP0 & ~OP1 & ~OP2 & OP3 & OP4 & ~OP5 ) begin
						next_sreg=`LDSP;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_RegWrite=1;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						RegSel= 'h1;
					end
					if ( ~OP0 & ~OP1 & ~OP2 & OP3 & ~OP4 & OP5 ) begin
						next_sreg=`STSP;
						next_SPWriteCond=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPWrite=1;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
					end
					if ( ~OP0 & ~OP1 & ~OP2 & ~OP3 & OP4 & ~OP5 ) begin
						next_sreg=`LDDS;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_RegWrite=1;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						RegSel= 'h0;
					end
					if ( ~OP0 & ~OP1 & ~OP2 & ~OP3 & OP4 & OP5 ) begin
						next_sreg=`STDS;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_DSSel=1;
						next_DSWrite=1;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
					end
					if ( OP0 & OP1 & ~OP2 & ~OP3 & ~OP4 & ~OP5 ) begin
						next_sreg=`STDSI;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_DSWrite=1;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
					end
					if ( ~OP0 & ~OP1 & ~OP2 & ~OP3 & OP4 & ~OP5 ) begin
						next_sreg=`EI;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IEBWrite=1;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
					end
					if ( ~OP0 & ~OP1 & ~OP2 & ~OP3 & ~OP4 & OP5 ) begin
						next_sreg=`DI;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IEBData=1;
						next_IEBWrite=1;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
					end
					if ( OP0 & OP1 & ~OP2 & ~OP3 & OP4 & ~OP5 ) begin
						next_sreg=`LD;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						SelMemAddr= 'h2;
					end
					if ( OP0 & OP1 & ~OP2 & ~OP3 & OP4 & OP5 ) begin
						next_sreg=`ST;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_MemWrite=1;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h1;
						SelMemAddr= 'h2;
					end
					if ( OP0 & ~OP1 & ~OP2 & ~OP3 & ~OP4 & ~OP5 ) begin
						next_sreg=`LDRI;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						SelMemAddr= 'h3;
					end
					if ( ~OP0 & OP1 & OP2 & ~OP3 & ~OP4 & ~OP5 | ~OP0 & ~OP1 & OP2 & OP3 & 
						~OP4 & ~OP5 ) begin
						next_sreg=`SPPlus2;
						next_SPWriteCond=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						next_SPWrite=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						ALUOp= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					if ( OP0 & ~OP1 & ~OP2 & ~OP3 & OP4 & OP5 ) begin
						next_sreg=`ADD;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						ALUOp= 'h0;
						ALUSrcB= 'h1;
						ALUSrcA= 'h2;
					end
					if ( OP0 & OP1 & ~OP2 & OP3 & OP4 & ~OP5 ) begin
						next_sreg=`ADDI;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						ALUOp= 'h0;
						ALUSrcB= 'h2;
						ALUSrcA= 'h2;
					end
					if ( OP0 & ~OP1 & ~OP2 & OP3 & ~OP4 & ~OP5 ) begin
						next_sreg=`SUB;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						ALUOp= 'h1;
						ALUSrcB= 'h1;
						ALUSrcA= 'h2;
					end
					if ( OP0 & OP1 & ~OP2 & OP3 & OP4 & OP5 ) begin
						next_sreg=`SUBI;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						ALUOp= 'h1;
						ALUSrcB= 'h1;
						ALUSrcA= 'h2;
					end
					if ( ~OP0 & ~OP1 & OP2 & OP3 & ~OP4 & OP5 ) begin
						next_sreg=`NEG;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						ALUOp= 'h1;
						ALUSrcB= 'h3;
						ALUSrcA= 'h3;
					end
					if ( OP0 & ~OP1 & ~OP2 & OP3 & ~OP4 & OP5 ) begin
						next_sreg=`intOR;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						ALUOp= 'h2;
						ALUSrcB= 'h1;
						ALUSrcA= 'h2;
					end
					if ( OP0 & OP1 & OP2 & ~OP3 & ~OP4 & ~OP5 ) begin
						next_sreg=`intORI;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						ALUOp= 'h2;
						ALUSrcB= 'h2;
						ALUSrcA= 'h2;
					end
					if ( OP0 & ~OP1 & ~OP2 & OP3 & OP4 & ~OP5 ) begin
						next_sreg=`intAND;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						ALUOp= 'h3;
						ALUSrcB= 'h1;
						ALUSrcA= 'h2;
					end
					if ( OP0 & OP1 & OP2 & ~OP3 & ~OP4 & OP5 ) begin
						next_sreg=`intANDI;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						ALUOp= 'h3;
						ALUSrcB= 'h2;
						ALUSrcA= 'h2;
					end
					if ( OP0 & ~OP1 & ~OP2 & OP3 & ~OP4 & OP5 ) begin
						next_sreg=`intSLL;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						ALUOp= 'h4;
						ALUSrcB= 'h1;
						ALUSrcA= 'h2;
					end
					if ( OP0 & OP1 & OP2 & ~OP3 & OP4 & ~OP5 ) begin
						next_sreg=`intSLLI;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						ALUOp= 'h4;
						ALUSrcB= 'h2;
						ALUSrcA= 'h2;
					end
					if ( OP0 & ~OP1 & ~OP2 & OP3 & OP4 & ~OP5 ) begin
						next_sreg=`intSLR;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						ALUOp= 'h5;
						ALUSrcB= 'h1;
						ALUSrcA= 'h2;
					end
					if ( OP0 & OP1 & OP2 & ~OP3 & OP4 & OP5 ) begin
						next_sreg=`intSLRI;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						ALUOp= 'h5;
						ALUSrcB= 'h2;
						ALUSrcA= 'h2;
					end
					if ( ~OP0 & OP1 & ~OP2 & OP3 & OP4 & ~OP5 ) begin
						next_sreg=`SPPlus2_C;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						next_SPWriteCond=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						ALUOp= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					if ( ~OP2 & OP5 & OP0 & ~OP1 & ~OP4 & ~OP3 & ~IRQ | ~OP1 & ~OP2 & ~OP4 &
						 ~OP5 & ~OP0 & ~IRQ | OP0 & OP4 & OP2 & ~OP1 & ~IRQ | ~OP1 & OP0 & OP3 & OP2 
						& ~IRQ | OP1 & OP2 & ~OP0 & OP5 & ~IRQ | OP2 & ~OP0 & OP3 & OP1 & ~IRQ | OP4 
						& OP3 & OP2 & ~IRQ ) begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
					if ( OP2 & OP4 & OP3 & IRQ | ~OP1 & ~OP2 & OP0 & OP5 & ~OP3 & ~OP4 & IRQ
						 | OP0 & ~OP1 & OP4 & OP2 & IRQ | ~OP1 & OP3 & OP0 & OP2 & IRQ | ~OP1 & ~OP2 
						& ~OP4 & ~OP5 & ~OP0 & IRQ | OP2 & OP1 & ~OP0 & OP5 & IRQ | OP2 & OP3 & ~OP0 
						& OP1 & IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
				end
				`DI : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`EI : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`Fetch : begin
					next_sreg=`Decode;
					next_SPWriteCond=0;
					next_SPWrite=0;
					next_SPSel=0;
					next_SelIntData=0;
					next_RegWrite=0;
					next_PCWriteCond=0;
					next_PCWrite=0;
					next_NegCond=0;
					next_IRWrite=0;
					next_IntWrite=0;
					next_IFetch=0;
					next_IEBWrite=0;
					next_IEBData=0;
					next_FlagsWrite=0;
					next_DSWrite=0;
					next_DSSel=0;
					next_DRWrite=0;
					next_ComboMux=0;
					next_MemWrite=1;
					ALUOp= 'h0;
					ALUSrcA= 'h0;
					ALUSrcB= 'h0;
					FlagsSel= 'h0;
					PCSel= 'h0;
					RegSel= 'h0;
					SelIntAddr= 'h0;
					SelMemData= 'h0;
					SelMemAddr= 'h1;
				end
				`GETI : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`intAND : begin
					next_sreg=`WriteBack_Sum;
					next_SPWriteCond=0;
					next_SPWrite=0;
					next_SPSel=0;
					next_SelIntData=0;
					next_PCWriteCond=0;
					next_PCWrite=0;
					next_NegCond=0;
					next_MemWrite=0;
					next_IRWrite=0;
					next_IntWrite=0;
					next_IFetch=0;
					next_IEBWrite=0;
					next_IEBData=0;
					next_FlagsWrite=0;
					next_DSWrite=0;
					next_DSSel=0;
					next_DRWrite=0;
					next_ComboMux=0;
					next_RegWrite=1;
					ALUOp= 'h0;
					ALUSrcA= 'h0;
					ALUSrcB= 'h0;
					FlagsSel= 'h0;
					PCSel= 'h0;
					SelIntAddr= 'h0;
					SelMemAddr= 'h0;
					SelMemData= 'h0;
					RegSel= 'h5;
				end
				`intANDI : begin
					next_sreg=`WriteBack_Sum;
					next_SPWriteCond=0;
					next_SPWrite=0;
					next_SPSel=0;
					next_SelIntData=0;
					next_PCWriteCond=0;
					next_PCWrite=0;
					next_NegCond=0;
					next_MemWrite=0;
					next_IRWrite=0;
					next_IntWrite=0;
					next_IFetch=0;
					next_IEBWrite=0;
					next_IEBData=0;
					next_FlagsWrite=0;
					next_DSWrite=0;
					next_DSSel=0;
					next_DRWrite=0;
					next_ComboMux=0;
					next_RegWrite=1;
					ALUOp= 'h0;
					ALUSrcA= 'h0;
					ALUSrcB= 'h0;
					FlagsSel= 'h0;
					PCSel= 'h0;
					SelIntAddr= 'h0;
					SelMemAddr= 'h0;
					SelMemData= 'h0;
					RegSel= 'h5;
				end
				`Interrupt_PC : begin
					next_sreg=`Fetch;
					next_SPWriteCond=0;
					next_SPWrite=0;
					next_SPSel=0;
					next_SelIntData=0;
					next_RegWrite=0;
					next_PCWriteCond=0;
					next_NegCond=0;
					next_MemWrite=0;
					next_IntWrite=0;
					next_IEBWrite=0;
					next_IEBData=0;
					next_FlagsWrite=0;
					next_DSWrite=0;
					next_DSSel=0;
					next_DRWrite=0;
					next_ComboMux=0;
					next_IRWrite=1;
					next_PCWrite=1;
					next_IFetch=1;
					FlagsSel= 'h0;
					RegSel= 'h0;
					SelIntAddr= 'h0;
					SelMemData= 'h0;
					PCSel= 'h0;
					ALUSrcB= 'h0;
					ALUSrcA= 'h0;
					ALUOp= 'h0;
					SelMemAddr= 'h0;
				end
				`Interrupt_Stack : begin
					next_sreg=`Interrupt_PC;
					next_SPWriteCond=0;
					next_SPWrite=0;
					next_SPSel=0;
					next_SelIntData=0;
					next_RegWrite=0;
					next_PCWriteCond=0;
					next_NegCond=0;
					next_MemWrite=0;
					next_IRWrite=0;
					next_IntWrite=0;
					next_IFetch=0;
					next_IEBWrite=0;
					next_IEBData=0;
					next_FlagsWrite=0;
					next_DSWrite=0;
					next_DSSel=0;
					next_DRWrite=0;
					next_ComboMux=0;
					next_PCWrite=1;
					ALUOp= 'h0;
					ALUSrcA= 'h0;
					ALUSrcB= 'h0;
					FlagsSel= 'h0;
					RegSel= 'h0;
					SelIntAddr= 'h0;
					SelMemAddr= 'h0;
					SelMemData= 'h0;
					PCSel= 'h4;
				end
				`intOR : begin
					next_sreg=`WriteBack_Sum;
					next_SPWriteCond=0;
					next_SPWrite=0;
					next_SPSel=0;
					next_SelIntData=0;
					next_PCWriteCond=0;
					next_PCWrite=0;
					next_NegCond=0;
					next_MemWrite=0;
					next_IRWrite=0;
					next_IntWrite=0;
					next_IFetch=0;
					next_IEBWrite=0;
					next_IEBData=0;
					next_FlagsWrite=0;
					next_DSWrite=0;
					next_DSSel=0;
					next_DRWrite=0;
					next_ComboMux=0;
					next_RegWrite=1;
					ALUOp= 'h0;
					ALUSrcA= 'h0;
					ALUSrcB= 'h0;
					FlagsSel= 'h0;
					PCSel= 'h0;
					SelIntAddr= 'h0;
					SelMemAddr= 'h0;
					SelMemData= 'h0;
					RegSel= 'h5;
				end
				`intORI : begin
					next_sreg=`WriteBack_Sum;
					next_SPWriteCond=0;
					next_SPWrite=0;
					next_SPSel=0;
					next_SelIntData=0;
					next_PCWriteCond=0;
					next_PCWrite=0;
					next_NegCond=0;
					next_MemWrite=0;
					next_IRWrite=0;
					next_IntWrite=0;
					next_IFetch=0;
					next_IEBWrite=0;
					next_IEBData=0;
					next_FlagsWrite=0;
					next_DSWrite=0;
					next_DSSel=0;
					next_DRWrite=0;
					next_ComboMux=0;
					next_RegWrite=1;
					ALUOp= 'h0;
					ALUSrcA= 'h0;
					ALUSrcB= 'h0;
					FlagsSel= 'h0;
					PCSel= 'h0;
					SelIntAddr= 'h0;
					SelMemAddr= 'h0;
					SelMemData= 'h0;
					RegSel= 'h5;
				end
				`intSLL : begin
					next_sreg=`WriteBack_Sum;
					next_SPWriteCond=0;
					next_SPWrite=0;
					next_SPSel=0;
					next_SelIntData=0;
					next_PCWriteCond=0;
					next_PCWrite=0;
					next_NegCond=0;
					next_MemWrite=0;
					next_IRWrite=0;
					next_IntWrite=0;
					next_IFetch=0;
					next_IEBWrite=0;
					next_IEBData=0;
					next_FlagsWrite=0;
					next_DSWrite=0;
					next_DSSel=0;
					next_DRWrite=0;
					next_ComboMux=0;
					next_RegWrite=1;
					ALUOp= 'h0;
					ALUSrcA= 'h0;
					ALUSrcB= 'h0;
					FlagsSel= 'h0;
					PCSel= 'h0;
					SelIntAddr= 'h0;
					SelMemAddr= 'h0;
					SelMemData= 'h0;
					RegSel= 'h5;
				end
				`intSLLI : begin
					next_sreg=`WriteBack_Sum;
					next_SPWriteCond=0;
					next_SPWrite=0;
					next_SPSel=0;
					next_SelIntData=0;
					next_PCWriteCond=0;
					next_PCWrite=0;
					next_NegCond=0;
					next_MemWrite=0;
					next_IRWrite=0;
					next_IntWrite=0;
					next_IFetch=0;
					next_IEBWrite=0;
					next_IEBData=0;
					next_FlagsWrite=0;
					next_DSWrite=0;
					next_DSSel=0;
					next_DRWrite=0;
					next_ComboMux=0;
					next_RegWrite=1;
					ALUOp= 'h0;
					ALUSrcA= 'h0;
					ALUSrcB= 'h0;
					FlagsSel= 'h0;
					PCSel= 'h0;
					SelIntAddr= 'h0;
					SelMemAddr= 'h0;
					SelMemData= 'h0;
					RegSel= 'h5;
				end
				`intSLR : begin
					next_sreg=`WriteBack_Sum;
					next_SPWriteCond=0;
					next_SPWrite=0;
					next_SPSel=0;
					next_SelIntData=0;
					next_PCWriteCond=0;
					next_PCWrite=0;
					next_NegCond=0;
					next_MemWrite=0;
					next_IRWrite=0;
					next_IntWrite=0;
					next_IFetch=0;
					next_IEBWrite=0;
					next_IEBData=0;
					next_FlagsWrite=0;
					next_DSWrite=0;
					next_DSSel=0;
					next_DRWrite=0;
					next_ComboMux=0;
					next_RegWrite=1;
					ALUOp= 'h0;
					ALUSrcA= 'h0;
					ALUSrcB= 'h0;
					FlagsSel= 'h0;
					PCSel= 'h0;
					SelIntAddr= 'h0;
					SelMemAddr= 'h0;
					SelMemData= 'h0;
					RegSel= 'h5;
				end
				`intSLRI : begin
					next_sreg=`WriteBack_Sum;
					next_SPWriteCond=0;
					next_SPWrite=0;
					next_SPSel=0;
					next_SelIntData=0;
					next_PCWriteCond=0;
					next_PCWrite=0;
					next_NegCond=0;
					next_MemWrite=0;
					next_IRWrite=0;
					next_IntWrite=0;
					next_IFetch=0;
					next_IEBWrite=0;
					next_IEBData=0;
					next_FlagsWrite=0;
					next_DSWrite=0;
					next_DSSel=0;
					next_DRWrite=0;
					next_ComboMux=0;
					next_RegWrite=1;
					ALUOp= 'h0;
					ALUSrcA= 'h0;
					ALUSrcB= 'h0;
					FlagsSel= 'h0;
					PCSel= 'h0;
					SelIntAddr= 'h0;
					SelMemAddr= 'h0;
					SelMemData= 'h0;
					RegSel= 'h5;
				end
				`JPA : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`JPC : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`JPNC : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`JPR : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`LD : begin
					next_sreg=`WriteBack_Mem;
					next_SPWriteCond=0;
					next_SPWrite=0;
					next_SPSel=0;
					next_SelIntData=0;
					next_PCWriteCond=0;
					next_PCWrite=0;
					next_NegCond=0;
					next_MemWrite=0;
					next_IRWrite=0;
					next_IntWrite=0;
					next_IFetch=0;
					next_IEBWrite=0;
					next_IEBData=0;
					next_FlagsWrite=0;
					next_DSWrite=0;
					next_DSSel=0;
					next_DRWrite=0;
					next_ComboMux=0;
					next_RegWrite=1;
					ALUOp= 'h0;
					ALUSrcA= 'h0;
					ALUSrcB= 'h0;
					FlagsSel= 'h0;
					PCSel= 'h0;
					SelIntAddr= 'h0;
					SelMemAddr= 'h0;
					SelMemData= 'h0;
					RegSel= 'h4;
				end
				`LDDR : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`LDDS : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`LDF : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`LDIL : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`LDIU : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`LDR : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`LDRI : begin
					next_sreg=`WriteBack_Mem;
					next_SPWriteCond=0;
					next_SPWrite=0;
					next_SPSel=0;
					next_SelIntData=0;
					next_PCWriteCond=0;
					next_PCWrite=0;
					next_NegCond=0;
					next_MemWrite=0;
					next_IRWrite=0;
					next_IntWrite=0;
					next_IFetch=0;
					next_IEBWrite=0;
					next_IEBData=0;
					next_FlagsWrite=0;
					next_DSWrite=0;
					next_DSSel=0;
					next_DRWrite=0;
					next_ComboMux=0;
					next_RegWrite=1;
					ALUOp= 'h0;
					ALUSrcA= 'h0;
					ALUSrcB= 'h0;
					FlagsSel= 'h0;
					PCSel= 'h0;
					SelIntAddr= 'h0;
					SelMemAddr= 'h0;
					SelMemData= 'h0;
					RegSel= 'h4;
				end
				`LDSP : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`NEG : begin
					next_sreg=`WriteBack_Sum;
					next_SPWriteCond=0;
					next_SPWrite=0;
					next_SPSel=0;
					next_SelIntData=0;
					next_PCWriteCond=0;
					next_PCWrite=0;
					next_NegCond=0;
					next_MemWrite=0;
					next_IRWrite=0;
					next_IntWrite=0;
					next_IFetch=0;
					next_IEBWrite=0;
					next_IEBData=0;
					next_FlagsWrite=0;
					next_DSWrite=0;
					next_DSSel=0;
					next_DRWrite=0;
					next_ComboMux=0;
					next_RegWrite=1;
					ALUOp= 'h0;
					ALUSrcA= 'h0;
					ALUSrcB= 'h0;
					FlagsSel= 'h0;
					PCSel= 'h0;
					SelIntAddr= 'h0;
					SelMemAddr= 'h0;
					SelMemData= 'h0;
					RegSel= 'h5;
				end
				`POP : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`PUSH : begin
					next_sreg=`SPMinus2;
					next_SPWriteCond=0;
					next_SPWrite=0;
					next_SPSel=0;
					next_SelIntData=0;
					next_RegWrite=0;
					next_PCWriteCond=0;
					next_PCWrite=0;
					next_NegCond=0;
					next_MemWrite=0;
					next_IRWrite=0;
					next_IntWrite=0;
					next_IFetch=0;
					next_IEBWrite=0;
					next_IEBData=0;
					next_FlagsWrite=0;
					next_DSWrite=0;
					next_DSSel=0;
					next_DRWrite=0;
					next_ComboMux=0;
					FlagsSel= 'h0;
					PCSel= 'h0;
					RegSel= 'h0;
					SelIntAddr= 'h0;
					SelMemAddr= 'h0;
					SelMemData= 'h0;
					ALUOp= 'h1;
					ALUSrcB= 'h0;
					ALUSrcA= 'h1;
				end
				`RESET1 : begin
					next_sreg=`RESET2;
					next_SPWriteCond=0;
					next_SPWrite=0;
					next_SPSel=0;
					next_SelIntData=0;
					next_RegWrite=0;
					next_PCWriteCond=0;
					next_PCWrite=0;
					next_NegCond=0;
					next_MemWrite=0;
					next_IRWrite=0;
					next_IntWrite=0;
					next_IFetch=0;
					next_IEBWrite=0;
					next_IEBData=0;
					next_FlagsWrite=0;
					next_DSWrite=0;
					next_DSSel=0;
					next_DRWrite=0;
					next_ComboMux=0;
					ALUOp= 'h0;
					ALUSrcA= 'h0;
					ALUSrcB= 'h0;
					FlagsSel= 'h0;
					PCSel= 'h0;
					RegSel= 'h0;
					SelIntAddr= 'h0;
					SelMemAddr= 'h0;
					SelMemData= 'h0;
				end
				`RESET2 : begin
					next_sreg=`Fetch;
					next_SPWriteCond=0;
					next_SPWrite=0;
					next_SPSel=0;
					next_SelIntData=0;
					next_RegWrite=0;
					next_PCWriteCond=0;
					next_NegCond=0;
					next_MemWrite=0;
					next_IntWrite=0;
					next_IEBWrite=0;
					next_IEBData=0;
					next_FlagsWrite=0;
					next_DSWrite=0;
					next_DSSel=0;
					next_DRWrite=0;
					next_ComboMux=0;
					next_IRWrite=1;
					next_PCWrite=1;
					next_IFetch=1;
					FlagsSel= 'h0;
					RegSel= 'h0;
					SelIntAddr= 'h0;
					SelMemData= 'h0;
					PCSel= 'h0;
					ALUSrcB= 'h0;
					ALUSrcA= 'h0;
					ALUOp= 'h0;
					SelMemAddr= 'h0;
				end
				`RETA : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`SETI : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`SETIA : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`SPMinus2 : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`SPPlus2 : begin
					if ( ~OP0 & OP1 & OP2 & ~OP3 & ~OP4 & ~OP5 ) begin
						next_sreg=`RETA;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_PCWrite=1;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h4;
						SelMemAddr= 'h1;
					end
					else begin
						next_sreg=`POP;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_RegWrite=1;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						FlagsSel= 'h0;
						PCSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						SelMemAddr= 'h1;
						RegSel= 'h4;
					end
				end
				`SPPlus2_C : begin
					if ( Cond ) begin
						next_sreg=`RETA;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_PCWrite=1;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h4;
						SelMemAddr= 'h1;
					end
					else if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`SPPlus2_NC : begin
					if ( Cond ) begin
						next_sreg=`RETA;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_PCWrite=1;
						ALUOp= 'h0;
						ALUSrcA= 'h0;
						ALUSrcB= 'h0;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h4;
						SelMemAddr= 'h1;
					end
					else if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`ST : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`STDR : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`STDS : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`STDSI : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`STF : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`STFI : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`STRI : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`STSP : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`SUB : begin
					next_sreg=`WriteBack_Sum;
					next_SPWriteCond=0;
					next_SPWrite=0;
					next_SPSel=0;
					next_SelIntData=0;
					next_PCWriteCond=0;
					next_PCWrite=0;
					next_NegCond=0;
					next_MemWrite=0;
					next_IRWrite=0;
					next_IntWrite=0;
					next_IFetch=0;
					next_IEBWrite=0;
					next_IEBData=0;
					next_FlagsWrite=0;
					next_DSWrite=0;
					next_DSSel=0;
					next_DRWrite=0;
					next_ComboMux=0;
					next_RegWrite=1;
					ALUOp= 'h0;
					ALUSrcA= 'h0;
					ALUSrcB= 'h0;
					FlagsSel= 'h0;
					PCSel= 'h0;
					SelIntAddr= 'h0;
					SelMemAddr= 'h0;
					SelMemData= 'h0;
					RegSel= 'h5;
				end
				`SUBI : begin
					next_sreg=`WriteBack_Sum;
					next_SPWriteCond=0;
					next_SPWrite=0;
					next_SPSel=0;
					next_SelIntData=0;
					next_PCWriteCond=0;
					next_PCWrite=0;
					next_NegCond=0;
					next_MemWrite=0;
					next_IRWrite=0;
					next_IntWrite=0;
					next_IFetch=0;
					next_IEBWrite=0;
					next_IEBData=0;
					next_FlagsWrite=0;
					next_DSWrite=0;
					next_DSSel=0;
					next_DRWrite=0;
					next_ComboMux=0;
					next_RegWrite=1;
					ALUOp= 'h0;
					ALUSrcA= 'h0;
					ALUSrcB= 'h0;
					FlagsSel= 'h0;
					PCSel= 'h0;
					SelIntAddr= 'h0;
					SelMemAddr= 'h0;
					SelMemData= 'h0;
					RegSel= 'h5;
				end
				`WriteBack_Comp : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`WriteBack_Mem : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
				`WriteBack_Sum : begin
					if ( IRQ ) begin
						next_sreg=`Interrupt_Stack;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_PCWrite=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IRWrite=0;
						next_IntWrite=0;
						next_IFetch=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_SPSel=1;
						FlagsSel= 'h0;
						PCSel= 'h0;
						RegSel= 'h0;
						SelMemAddr= 'h0;
						SelMemData= 'h0;
						SelIntAddr= 'h2;
						ALUOp= 'h1;
						ALUSrcB= 'h0;
						ALUSrcA= 'h1;
					end
					else begin
						next_sreg=`Fetch;
						next_SPWriteCond=0;
						next_SPWrite=0;
						next_SPSel=0;
						next_SelIntData=0;
						next_RegWrite=0;
						next_PCWriteCond=0;
						next_NegCond=0;
						next_MemWrite=0;
						next_IntWrite=0;
						next_IEBWrite=0;
						next_IEBData=0;
						next_FlagsWrite=0;
						next_DSWrite=0;
						next_DSSel=0;
						next_DRWrite=0;
						next_ComboMux=0;
						next_IRWrite=1;
						next_PCWrite=1;
						next_IFetch=1;
						FlagsSel= 'h0;
						RegSel= 'h0;
						SelIntAddr= 'h0;
						SelMemData= 'h0;
						PCSel= 'h0;
						ALUSrcB= 'h0;
						ALUSrcA= 'h0;
						ALUOp= 'h0;
						SelMemAddr= 'h0;
					end
				end
			endcase
		end

		next_ALUOp2 = ALUOp[2];
		next_ALUOp1 = ALUOp[1];
		next_ALUOp0 = ALUOp[0];
		next_ALUSrcA1 = ALUSrcA[1];
		next_ALUSrcA0 = ALUSrcA[0];
		next_ALUSrcB1 = ALUSrcB[1];
		next_ALUSrcB0 = ALUSrcB[0];
		next_FlagsSel1 = FlagsSel[1];
		next_FlagsSel0 = FlagsSel[0];
		next_PCSel2 = PCSel[2];
		next_PCSel1 = PCSel[1];
		next_PCSel0 = PCSel[0];
		next_RegSel3 = RegSel[3];
		next_RegSel2 = RegSel[2];
		next_RegSel1 = RegSel[1];
		next_RegSel0 = RegSel[0];
		next_SelIntAddr1 = SelIntAddr[1];
		next_SelIntAddr0 = SelIntAddr[0];
		next_SelMemAddr2 = SelMemAddr[2];
		next_SelMemAddr1 = SelMemAddr[1];
		next_SelMemAddr0 = SelMemAddr[0];
		next_SelMemData1 = SelMemData[1];
		next_SelMemData0 = SelMemData[0];
	end
endmodule

module control(ALUOp,ALUSrcA,ALUSrcB,FlagsSel,OP,PCSel,RegSel,SelIntAddr,
	SelMemAddr,SelMemData,CLK,Cond,IRQ,RESET,ComboMux,DRWrite,DSSel,DSWrite,
	FlagsWrite,IEBData,IEBWrite,IFetch,IntWrite,IRWrite,MemWrite,NegCond,PCWrite,
	PCWriteCond,RegWrite,SelIntData,SPSel,SPWrite,SPWriteCond);

	output [2:0] ALUOp;
	output [1:0] ALUSrcA;
	output [1:0] ALUSrcB;
	output [1:0] FlagsSel;
	input [5:0] OP;
	output [2:0] PCSel;
	output [3:0] RegSel;
	output [1:0] SelIntAddr;
	output [2:0] SelMemAddr;
	output [1:0] SelMemData;
	input CLK;
	input Cond,IRQ,RESET;
	output ComboMux,DRWrite,DSSel,DSWrite,FlagsWrite,IEBData,IEBWrite,IFetch,
		IntWrite,IRWrite,MemWrite,NegCond,PCWrite,PCWriteCond,RegWrite,SelIntData,
		SPSel,SPWrite,SPWriteCond;

	wire [2:0] ALUOp;
	wire [1:0] ALUSrcA;
	wire [1:0] ALUSrcB;
	wire [1:0] FlagsSel;
	wire [5:0] OP;
	wire [2:0] PCSel;
	wire [3:0] RegSel;
	wire [1:0] SelIntAddr;
	wire [2:0] SelMemAddr;
	wire [1:0] SelMemData;
	wire CLK;
	wire Cond,IRQ,RESET;
	wire ComboMux,DRWrite,DSSel,DSWrite,FlagsWrite,IEBData,IEBWrite,IFetch,
		IntWrite,IRWrite,MemWrite,NegCond,PCWrite,PCWriteCond,RegWrite,SelIntData,
		SPSel,SPWrite,SPWriteCond;

	shell_control part1(.CLK(CLK),.Cond(Cond),.IRQ(IRQ),.OP0(OP[0]),.OP1(OP[1]),
		.OP2(OP[2]),.OP3(OP[3]),.OP4(OP[4]),.OP5(OP[5]),.RESET(RESET),.ALUOp0(
		ALUOp[0]),.ALUOp1(ALUOp[1]),.ALUOp2(ALUOp[2]),.ALUSrcA0(ALUSrcA[0]),.ALUSrcA1
		(ALUSrcA[1]),.ALUSrcB0(ALUSrcB[0]),.ALUSrcB1(ALUSrcB[1]),.ComboMux(ComboMux),
		.DRWrite(DRWrite),.DSSel(DSSel),.DSWrite(DSWrite),.FlagsSel0(FlagsSel[0]),
		.FlagsSel1(FlagsSel[1]),.FlagsWrite(FlagsWrite),.IEBData(IEBData),.IEBWrite(
		IEBWrite),.IFetch(IFetch),.IntWrite(IntWrite),.IRWrite(IRWrite),.MemWrite(
		MemWrite),.NegCond(NegCond),.PCSel0(PCSel[0]),.PCSel1(PCSel[1]),.PCSel2(
		PCSel[2]),.PCWrite(PCWrite),.PCWriteCond(PCWriteCond),.RegSel0(RegSel[0]),
		.RegSel1(RegSel[1]),.RegSel2(RegSel[2]),.RegSel3(RegSel[3]),.RegWrite(
		RegWrite),.SelIntAddr0(SelIntAddr[0]),.SelIntAddr1(SelIntAddr[1]),.SelIntData
		(SelIntData),.SelMemAddr0(SelMemAddr[0]),.SelMemAddr1(SelMemAddr[1]),
		.SelMemAddr2(SelMemAddr[2]),.SelMemData0(SelMemData[0]),.SelMemData1(
		SelMemData[1]),.SPSel(SPSel),.SPWrite(SPWrite),.SPWriteCond(SPWriteCond));


endmodule
