/*********************************************************/
// MODULE:			RegFile
//
// FILE NAME:		RegFile.v
// VERSION:			1.1
// DATE:				Created Feb 9, 2003
//                Modified Nov 15, 2003 by Larry Merkle
//                - "Unregistered" ReadDataN to eliminate
//                  the clock cycle delay between changing 
//                  ReadRegN and seeing the effect on ReadDataN
// AUTHOR:			Larry Merkle
//
// DESCRIPTION:	This module defines a register file with 
//                eight 16-bit registers, two read ports, 
//                and one write port.  
//
/*********************************************************/
module RegFile(
   ReadReg1,
   ReadReg2,
   WriteReg,
   WriteData,
   RegWrite,
   ReadData1,               
   ReadData2,
   CLK);

// Definitions

parameter NUM_REGS = 4;
`define ADDR_SZ 2
`define REG_WIDTH 16

// Inputs

input [`ADDR_SZ-1:0] ReadReg1;
input [`ADDR_SZ-1:0] ReadReg2;
input [`ADDR_SZ-1:0] WriteReg;
input [`REG_WIDTH-1:0] WriteData;
input RegWrite;
input CLK;

// Outputs

output [`REG_WIDTH-1:0] ReadData1;
output [`REG_WIDTH-1:0] ReadData2;

// Signals

wire [`REG_WIDTH-1:0] ReadData1;
wire [`REG_WIDTH-1:0] ReadData2;

// The registers

reg [`REG_WIDTH-1:0] Reg [NUM_REGS-1:0];

assign ReadData1 = Reg[ ReadReg1 ];
assign ReadData2 = Reg[ ReadReg2 ];

// Operation

always @ ( posedge CLK ) begin
   if ( RegWrite )
      Reg[ WriteReg ] <= WriteData;
end

endmodule
