library verilog;
use verilog.vl_types.all;
entity busmux is
    port(
        d0              : in     vl_logic_vector(15 downto 0);
        d1              : in     vl_logic_vector(15 downto 0);
        d2              : in     vl_logic_vector(15 downto 0);
        d3              : in     vl_logic_vector(15 downto 0);
        d4              : in     vl_logic_vector(15 downto 0);
        d5              : in     vl_logic_vector(15 downto 0);
        d6              : in     vl_logic_vector(15 downto 0);
        d7              : in     vl_logic_vector(15 downto 0);
        d8              : in     vl_logic_vector(15 downto 0);
        d9              : in     vl_logic_vector(15 downto 0);
        d10             : in     vl_logic_vector(15 downto 0);
        d11             : in     vl_logic_vector(15 downto 0);
        d12             : in     vl_logic_vector(15 downto 0);
        d13             : in     vl_logic_vector(15 downto 0);
        d14             : in     vl_logic_vector(15 downto 0);
        d15             : in     vl_logic_vector(15 downto 0);
        s               : in     vl_logic_vector(3 downto 0);
        o               : out    vl_logic_vector(15 downto 0)
    );
end busmux;
