library verilog;
use verilog.vl_types.all;
entity ofdx16_mxilinx_reg1 is
    port(
        c               : in     vl_logic;
        ce              : in     vl_logic;
        d               : in     vl_logic_vector(15 downto 0);
        q               : out    vl_logic_vector(15 downto 0)
    );
end ofdx16_mxilinx_reg1;
