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// The synopsys directives "translate_off/translate_on" specified below are
// supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).

// You must compile the wrapper file concatmux.v when simulating
// the core, concatmux. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Guide".

module concatmux (
	MA,
	MB,
	S,
	O);    // synthesis black_box

input [7 : 0] MA;
input [7 : 0] MB;
input [0 : 0] S;
output [7 : 0] O;

// synopsys translate_off

	C_MUX_BUS_V6_0 #(
		"00000000",	// c_ainit_val
		0,	// c_enable_rlocs
		0,	// c_has_aclr
		0,	// c_has_ainit
		0,	// c_has_aset
		0,	// c_has_ce
		0,	// c_has_en
		1,	// c_has_o
		0,	// c_has_q
		0,	// c_has_sclr
		0,	// c_has_sinit
		0,	// c_has_sset
		0,	// c_height
		2,	// c_inputs
		0,	// c_latency
		0,	// c_mux_type
		1,	// c_sel_width
		"00000000",	// c_sinit_val
		0,	// c_sync_enable
		1,	// c_sync_priority
		8)	// c_width
	inst (
		.MA(MA),
		.MB(MB),
		.S(S),
		.O(O),
		.MH(),
		.MG(),
		.MF(),
		.ME(),
		.MD(),
		.MC(),
		.MAH(),
		.MAG(),
		.MAF(),
		.MAE(),
		.MAD(),
		.MAC(),
		.MAB(),
		.MAA(),
		.MBH(),
		.MBG(),
		.MBF(),
		.MBE(),
		.MBD(),
		.MBC(),
		.MBB(),
		.MBA(),
		.MCH(),
		.MCG(),
		.MCF(),
		.MCE(),
		.MCD(),
		.MCC(),
		.MCB(),
		.MCA(),
		.CE(),
		.CLK(),
		.ASET(),
		.SSET(),
		.EN(),
		.ACLR(),
		.SCLR(),
		.AINIT(),
		.SINIT(),
		.Q());


// synopsys translate_on

// FPGA Express black box declaration
// synopsys attribute fpga_dont_touch "true"
// synthesis attribute fpga_dont_touch of concatmux is "true"

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of concatmux is "black_box"

endmodule

