library verilog;
use verilog.vl_types.all;
entity regfile1 is
    port(
        clock           : in     vl_logic;
        reada           : in     vl_logic_vector(3 downto 0);
        readb           : in     vl_logic_vector(3 downto 0);
        regwrite        : in     vl_logic;
        writeaddress    : in     vl_logic_vector(3 downto 0);
        writedata       : in     vl_logic_vector(15 downto 0);
        outa            : out    vl_logic_vector(15 downto 0);
        outb            : out    vl_logic_vector(15 downto 0)
    );
end regfile1;
