# Xilinx CORE Generator 6.1.03i; Cores Update # 1
# Username = carusobp
# COREGenPath = C:\Xilinx\coregen
# ProjectPath = C:\Xilinx\RegALU
# ExpandedProjectPath = C:\Xilinx\RegALU
# OverwriteFiles = true
# Core name: concatmux
# Number of Primitives in design: 8
# Number of CLBs used in design cannot be determined when there is no RPMed logic
# Number of Slices used in design cannot be determined when there is no RPMed logic
# Number of LUT sites used in design: 8
# Number of LUTs used in design: 8
# Number of REG used in design: 0
# Number of SRL16s used in design: 0
# Number of Distributed RAM primitives used in design: 0
# Number of Block Memories used in design: 0
# Number of Dedicated Multipliers used in design: 0
# Number of HU_SETs used: 0
# 
SET BusFormat = BusFormatAngleBracketNotRipped
SET XilinxFamily = Spartan2
SET OutputOption = OutputProducts
SET FlowVendor = Foundation_iSE
SET FormalVerification = None
SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim
SELECT Bus_Multiplexer Spartan2 Xilinx,_Inc. 6.0
CSET output_enable = false
CSET async_init_value = 0
CSET set_clear_priority = clear_overrides_set
CSET ce_overrides = sync_controls_override_ce
CSET output_options = non_registered
CSET sync_init_value = 0
CSET clock_enable = false
CSET create_rpm = false
CSET multiplexer_construction = lut_based
CSET asynchronous_settings = none
CSET synchronous_settings = none
CSET input_bus_width = 8
CSET component_name = concatmux
CSET latency = 0
CSET number_of_input_buses = 2
GENERATE

