library verilog;
use verilog.vl_types.all;
entity jumpconcat is
    port(
        pcin            : in     vl_logic_vector(15 downto 0);
        shiftin         : in     vl_logic_vector(15 downto 0);
        concatout       : out    vl_logic_vector(15 downto 0)
    );
end jumpconcat;
