library verilog;
use verilog.vl_types.all;
entity ripple_adder is
    port(
        a               : in     vl_logic;
        b               : in     vl_logic;
        carryin         : in     vl_logic;
        carryout        : out    vl_logic;
        sum             : out    vl_logic
    );
end ripple_adder;
