library verilog;
use verilog.vl_types.all;
entity irreg is
    port(
        d               : in     vl_logic_vector(15 downto 0);
        q               : out    vl_logic_vector(15 downto 0);
        clk             : in     vl_logic;
        ce              : in     vl_logic
    );
end irreg;
