library verilog;
use verilog.vl_types.all;
entity reg1 is
    port(
        clock           : in     vl_logic;
        din             : in     vl_logic_vector(15 downto 0);
        writeenable     : in     vl_logic;
        qout            : out    vl_logic_vector(15 downto 0)
    );
end reg1;
