library verilog;
use verilog.vl_types.all;
entity twobusmux4bit is
    port(
        ma              : in     vl_logic_vector(3 downto 0);
        mb              : in     vl_logic_vector(3 downto 0);
        s               : in     vl_logic_vector(0 downto 0);
        o               : out    vl_logic_vector(3 downto 0)
    );
end twobusmux4bit;
