library verilog;
use verilog.vl_types.all;
entity circuit is
    port(
        alu_a           : in     vl_logic_vector(1 downto 0);
        alu_b           : in     vl_logic_vector(1 downto 0);
        a_select        : in     vl_logic_vector(0 downto 0);
        clock           : in     vl_logic;
        irwrite         : in     vl_logic;
        ir_input        : in     vl_logic_vector(15 downto 0);
        pcselect        : in     vl_logic_vector(1 downto 0);
        regdata         : in     vl_logic_vector(2 downto 0);
        regreadb        : in     vl_logic_vector(0 downto 0);
        regwrite        : in     vl_logic;
        toreg           : in     vl_logic_vector(1 downto 0);
        alu_output      : out    vl_logic_vector(15 downto 0);
        a_output        : out    vl_logic_vector(15 downto 0);
        b_output        : out    vl_logic_vector(15 downto 0);
        pcinput         : out    vl_logic_vector(15 downto 0)
    );
end circuit;
