[COREGEN.VERILOG Component Instantiation.a]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="a YourInstanceName ("
text007="    .D(D),"
text008="    .Q(Q),"
text009="    .CLK(CLK));"
text010=""
text011=" "
type=template
[COREGEN.VERILOG Component Instantiation.alu_mux]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="alu_mux YourInstanceName ("
text007="    .MA(MA),"
text008="    .MB(MB),"
text009="    .MC(MC),"
text010="    .MD(MD),"
text011="    .ME(ME),"
text012="    .S(S),"
text013="    .O(O));"
text014=""
text015=" "
type=template
[COREGEN.VERILOG Component Instantiation.AtempMux]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="atempmux YourInstanceName ("
text007="    .MA(MA),"
text008="    .MB(MB),"
text009="    .S(S),"
text010="    .O(O));"
text011=""
text012=" "
type=template
[COREGEN.VERILOG Component Instantiation.b]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="b YourInstanceName ("
text007="    .D(D),"
text008="    .Q(Q),"
text009="    .CLK(CLK));"
text010=""
text011=" "
type=template
[COREGEN.VERILOG Component Instantiation.balumux]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="balumux YourInstanceName ("
text007="    .MA(MA),"
text008="    .MB(MB),"
text009="    .MC(MC),"
text010="    .MD(MD),"
text011="    .S(S),"
text012="    .O(O));"
text013=""
text014=" "
type=template
[COREGEN.VERILOG Component Instantiation.bit_adder]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="bit_adder YourInstanceName ("
text007="    .A(A),"
text008="    .B(B),"
text009="    .C_IN(C_IN),"
text010="    .C_OUT(C_OUT),"
text011="    .S(S));"
text012=""
text013=" "
type=template
[COREGEN.VERILOG Component Instantiation.concatmux]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="concatmux YourInstanceName ("
text007="    .MA(MA),"
text008="    .MB(MB),"
text009="    .S(S),"
text010="    .O(O));"
text011=""
text012=" "
type=template
[COREGEN.VERILOG Component Instantiation.EPC]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="epc YourInstanceName ("
text007="    .D(D),"
text008="    .Q(Q),"
text009="    .CLK(CLK),"
text010="    .CE(CE));"
text011=""
text012=" "
type=template
[COREGEN.VERILOG Component Instantiation.FiveBusMux]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="fivebusmux YourInstanceName ("
text007="    .MA(MA),"
text008="    .MB(MB),"
text009="    .MC(MC),"
text010="    .MD(MD),"
text011="    .ME(ME),"
text012="    .S(S),"
text013="    .O(O));"
text014=""
text015=" "
type=template
[COREGEN.VERILOG Component Instantiation.fivebusmux4bit]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="fivebusmux4bit YourInstanceName ("
text007="    .MA(MA),"
text008="    .MB(MB),"
text009="    .MC(MC),"
text010="    .MD(MD),"
text011="    .ME(ME),"
text012="    .S(S),"
text013="    .O(O));"
text014=""
text015=" "
type=template
[COREGEN.VERILOG Component Instantiation.fourbusmux4bit]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="fourbusmux4bit YourInstanceName ("
text007="    .MA(MA),"
text008="    .MB(MB),"
text009="    .MC(MC),"
text010="    .MD(MD),"
text011="    .S(S),"
text012="    .O(O));"
text013=""
text014=" "
type=template
[COREGEN.VERILOG Component Instantiation.inputreg]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="inputreg YourInstanceName ("
text007="    .D(D),"
text008="    .Q(Q),"
text009="    .CLK(CLK));"
text010=""
text011=" "
type=template
[COREGEN.VERILOG Component Instantiation.int]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="int YourInstanceName ("
text007="    .D(D),"
text008="    .Q(Q),"
text009="    .CLK(CLK));"
text010=""
text011=" "
type=template
[COREGEN.VERILOG Component Instantiation.PC]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="pc YourInstanceName ("
text007="    .D(D),"
text008="    .Q(Q),"
text009="    .CLK(CLK),"
text010="    .CE(CE));"
text011=""
text012=" "
type=template
[COREGEN.VERILOG Component Instantiation.PROCFLAG]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="procflag YourInstanceName ("
text007="    .D(D),"
text008="    .Q(Q),"
text009="    .CLK(CLK),"
text010="    .CE(CE));"
text011=""
text012=" "
type=template
[COREGEN.VERILOG Component Instantiation.shiftmuxone]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="shiftmuxone YourInstanceName ("
text007="    .MA(MA),"
text008="    .MB(MB),"
text009="    .S(S),"
text010="    .O(O));"
text011=""
text012=" "
type=template
[COREGEN.VERILOG Component Instantiation.sixbusmux]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="sixbusmux YourInstanceName ("
text007="    .MA(MA),"
text008="    .MB(MB),"
text009="    .MC(MC),"
text010="    .MD(MD),"
text011="    .ME(ME),"
text012="    .MF(MF),"
text013="    .S(S),"
text014="    .O(O));"
text015=""
text016=" "
type=template
[COREGEN.VERILOG Component Instantiation.ThreeBusMux16bit]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="threebusmux16bit YourInstanceName ("
text007="    .MA(MA),"
text008="    .MB(MB),"
text009="    .MC(MC),"
text010="    .S(S),"
text011="    .O(O));"
text012=""
text013=" "
type=template
[COREGEN.VERILOG Component Instantiation.TwoBusMux16bit]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="twobusmux16bit YourInstanceName ("
text007="    .MA(MA),"
text008="    .MB(MB),"
text009="    .S(S),"
text010="    .O(O));"
text011=""
text012=" "
type=template
[COREGEN.VERILOG Component Instantiation.TwoBusMux4bit]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="twobusmux4bit YourInstanceName ("
text007="    .MA(MA),"
text008="    .MB(MB),"
text009="    .S(S),"
text010="    .O(O));"
text011=""
text012=" "
type=template
[COREGEN.VHDL Component Instantiation.a]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component a"
text005="    port ("
text006="    D: IN std_logic_VECTOR(15 downto 0);"
text007="    Q: OUT std_logic_VECTOR(15 downto 0);"
text008="    CLK: IN std_logic);"
text009="end component;"
text010=""
text011=""
text012=""
text013=" "
text014="-------------------------------------------------------------"
text015=" "
text016="-- The following code must appear in the VHDL architecture body."
text017="-- Substitute your own instance name and net names."
text018=" "
text019="your_instance_name : a"
text020="        port map ("
text021="            D => D,"
text022="            Q => Q,"
text023="            CLK => CLK);"
text024=" "
type=template
[COREGEN.VHDL Component Instantiation.alu_mux]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component alu_mux"
text005="    port ("
text006="    MA: IN std_logic_VECTOR(15 downto 0);"
text007="    MB: IN std_logic_VECTOR(15 downto 0);"
text008="    MC: IN std_logic_VECTOR(15 downto 0);"
text009="    MD: IN std_logic_VECTOR(15 downto 0);"
text010="    ME: IN std_logic_VECTOR(15 downto 0);"
text011="    S: IN std_logic_VECTOR(2 downto 0);"
text012="    O: OUT std_logic_VECTOR(15 downto 0));"
text013="end component;"
text014=""
text015=""
text016=""
text017=" "
text018="-------------------------------------------------------------"
text019=" "
text020="-- The following code must appear in the VHDL architecture body."
text021="-- Substitute your own instance name and net names."
text022=" "
text023="your_instance_name : alu_mux"
text024="        port map ("
text025="            MA => MA,"
text026="            MB => MB,"
text027="            MC => MC,"
text028="            MD => MD,"
text029="            ME => ME,"
text030="            S => S,"
text031="            O => O);"
text032=" "
type=template
[COREGEN.VHDL Component Instantiation.AtempMux]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component atempmux"
text005="    port ("
text006="    MA: IN std_logic_VECTOR(15 downto 0);"
text007="    MB: IN std_logic_VECTOR(15 downto 0);"
text008="    S: IN std_logic_VECTOR(0 downto 0);"
text009="    O: OUT std_logic_VECTOR(15 downto 0));"
text010="end component;"
text011=""
text012=""
text013=""
text014=" "
text015="-------------------------------------------------------------"
text016=" "
text017="-- The following code must appear in the VHDL architecture body."
text018="-- Substitute your own instance name and net names."
text019=" "
text020="your_instance_name : atempmux"
text021="        port map ("
text022="            MA => MA,"
text023="            MB => MB,"
text024="            S => S,"
text025="            O => O);"
text026=" "
type=template
[COREGEN.VHDL Component Instantiation.b]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component b"
text005="    port ("
text006="    D: IN std_logic_VECTOR(15 downto 0);"
text007="    Q: OUT std_logic_VECTOR(15 downto 0);"
text008="    CLK: IN std_logic);"
text009="end component;"
text010=""
text011=""
text012=""
text013=" "
text014="-------------------------------------------------------------"
text015=" "
text016="-- The following code must appear in the VHDL architecture body."
text017="-- Substitute your own instance name and net names."
text018=" "
text019="your_instance_name : b"
text020="        port map ("
text021="            D => D,"
text022="            Q => Q,"
text023="            CLK => CLK);"
text024=" "
type=template
[COREGEN.VHDL Component Instantiation.balumux]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component balumux"
text005="    port ("
text006="    MA: IN std_logic_VECTOR(15 downto 0);"
text007="    MB: IN std_logic_VECTOR(15 downto 0);"
text008="    MC: IN std_logic_VECTOR(15 downto 0);"
text009="    MD: IN std_logic_VECTOR(15 downto 0);"
text010="    S: IN std_logic_VECTOR(1 downto 0);"
text011="    O: OUT std_logic_VECTOR(15 downto 0));"
text012="end component;"
text013=""
text014=""
text015=""
text016=" "
text017="-------------------------------------------------------------"
text018=" "
text019="-- The following code must appear in the VHDL architecture body."
text020="-- Substitute your own instance name and net names."
text021=" "
text022="your_instance_name : balumux"
text023="        port map ("
text024="            MA => MA,"
text025="            MB => MB,"
text026="            MC => MC,"
text027="            MD => MD,"
text028="            S => S,"
text029="            O => O);"
text030=" "
type=template
[COREGEN.VHDL Component Instantiation.bit_adder]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component bit_adder"
text005="    port ("
text006="    A: IN std_logic_VECTOR(0 downto 0);"
text007="    B: IN std_logic_VECTOR(0 downto 0);"
text008="    C_IN: IN std_logic;"
text009="    C_OUT: OUT std_logic;"
text010="    S: OUT std_logic_VECTOR(0 downto 0));"
text011="end component;"
text012=""
text013=""
text014=""
text015=" "
text016="-------------------------------------------------------------"
text017=" "
text018="-- The following code must appear in the VHDL architecture body."
text019="-- Substitute your own instance name and net names."
text020=" "
text021="your_instance_name : bit_adder"
text022="        port map ("
text023="            A => A,"
text024="            B => B,"
text025="            C_IN => C_IN,"
text026="            C_OUT => C_OUT,"
text027="            S => S);"
text028=" "
type=template
[COREGEN.VHDL Component Instantiation.concatmux]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component concatmux"
text005="    port ("
text006="    MA: IN std_logic_VECTOR(7 downto 0);"
text007="    MB: IN std_logic_VECTOR(7 downto 0);"
text008="    S: IN std_logic_VECTOR(0 downto 0);"
text009="    O: OUT std_logic_VECTOR(7 downto 0));"
text010="end component;"
text011=""
text012=""
text013=""
text014=" "
text015="-------------------------------------------------------------"
text016=" "
text017="-- The following code must appear in the VHDL architecture body."
text018="-- Substitute your own instance name and net names."
text019=" "
text020="your_instance_name : concatmux"
text021="        port map ("
text022="            MA => MA,"
text023="            MB => MB,"
text024="            S => S,"
text025="            O => O);"
text026=" "
type=template
[COREGEN.VHDL Component Instantiation.EPC]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component epc"
text005="    port ("
text006="    D: IN std_logic_VECTOR(15 downto 0);"
text007="    Q: OUT std_logic_VECTOR(15 downto 0);"
text008="    CLK: IN std_logic;"
text009="    CE: IN std_logic);"
text010="end component;"
text011=""
text012=""
text013=""
text014=" "
text015="-------------------------------------------------------------"
text016=" "
text017="-- The following code must appear in the VHDL architecture body."
text018="-- Substitute your own instance name and net names."
text019=" "
text020="your_instance_name : epc"
text021="        port map ("
text022="            D => D,"
text023="            Q => Q,"
text024="            CLK => CLK,"
text025="            CE => CE);"
text026=" "
type=template
[COREGEN.VHDL Component Instantiation.FiveBusMux]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component fivebusmux"
text005="    port ("
text006="    MA: IN std_logic_VECTOR(15 downto 0);"
text007="    MB: IN std_logic_VECTOR(15 downto 0);"
text008="    MC: IN std_logic_VECTOR(15 downto 0);"
text009="    MD: IN std_logic_VECTOR(15 downto 0);"
text010="    ME: IN std_logic_VECTOR(15 downto 0);"
text011="    S: IN std_logic_VECTOR(2 downto 0);"
text012="    O: OUT std_logic_VECTOR(15 downto 0));"
text013="end component;"
text014=""
text015=""
text016=""
text017=" "
text018="-------------------------------------------------------------"
text019=" "
text020="-- The following code must appear in the VHDL architecture body."
text021="-- Substitute your own instance name and net names."
text022=" "
text023="your_instance_name : fivebusmux"
text024="        port map ("
text025="            MA => MA,"
text026="            MB => MB,"
text027="            MC => MC,"
text028="            MD => MD,"
text029="            ME => ME,"
text030="            S => S,"
text031="            O => O);"
text032=" "
type=template
[COREGEN.VHDL Component Instantiation.fivebusmux4bit]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component fivebusmux4bit"
text005="    port ("
text006="    MA: IN std_logic_VECTOR(3 downto 0);"
text007="    MB: IN std_logic_VECTOR(3 downto 0);"
text008="    MC: IN std_logic_VECTOR(3 downto 0);"
text009="    MD: IN std_logic_VECTOR(3 downto 0);"
text010="    ME: IN std_logic_VECTOR(3 downto 0);"
text011="    S: IN std_logic_VECTOR(2 downto 0);"
text012="    O: OUT std_logic_VECTOR(3 downto 0));"
text013="end component;"
text014=""
text015=""
text016=""
text017=" "
text018="-------------------------------------------------------------"
text019=" "
text020="-- The following code must appear in the VHDL architecture body."
text021="-- Substitute your own instance name and net names."
text022=" "
text023="your_instance_name : fivebusmux4bit"
text024="        port map ("
text025="            MA => MA,"
text026="            MB => MB,"
text027="            MC => MC,"
text028="            MD => MD,"
text029="            ME => ME,"
text030="            S => S,"
text031="            O => O);"
text032=" "
type=template
[COREGEN.VHDL Component Instantiation.fourbusmux4bit]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component fourbusmux4bit"
text005="    port ("
text006="    MA: IN std_logic_VECTOR(3 downto 0);"
text007="    MB: IN std_logic_VECTOR(3 downto 0);"
text008="    MC: IN std_logic_VECTOR(3 downto 0);"
text009="    MD: IN std_logic_VECTOR(3 downto 0);"
text010="    S: IN std_logic_VECTOR(1 downto 0);"
text011="    O: OUT std_logic_VECTOR(3 downto 0));"
text012="end component;"
text013=""
text014=""
text015=""
text016=" "
text017="-------------------------------------------------------------"
text018=" "
text019="-- The following code must appear in the VHDL architecture body."
text020="-- Substitute your own instance name and net names."
text021=" "
text022="your_instance_name : fourbusmux4bit"
text023="        port map ("
text024="            MA => MA,"
text025="            MB => MB,"
text026="            MC => MC,"
text027="            MD => MD,"
text028="            S => S,"
text029="            O => O);"
text030=" "
type=template
[COREGEN.VHDL Component Instantiation.inputreg]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component inputreg"
text005="    port ("
text006="    D: IN std_logic_VECTOR(15 downto 0);"
text007="    Q: OUT std_logic_VECTOR(15 downto 0);"
text008="    CLK: IN std_logic);"
text009="end component;"
text010=""
text011=""
text012=""
text013=" "
text014="-------------------------------------------------------------"
text015=" "
text016="-- The following code must appear in the VHDL architecture body."
text017="-- Substitute your own instance name and net names."
text018=" "
text019="your_instance_name : inputreg"
text020="        port map ("
text021="            D => D,"
text022="            Q => Q,"
text023="            CLK => CLK);"
text024=" "
type=template
[COREGEN.VHDL Component Instantiation.int]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component int"
text005="    port ("
text006="    D: IN std_logic_VECTOR(0 downto 0);"
text007="    Q: OUT std_logic_VECTOR(0 downto 0);"
text008="    CLK: IN std_logic);"
text009="end component;"
text010=""
text011=""
text012=""
text013=" "
text014="-------------------------------------------------------------"
text015=" "
text016="-- The following code must appear in the VHDL architecture body."
text017="-- Substitute your own instance name and net names."
text018=" "
text019="your_instance_name : int"
text020="        port map ("
text021="            D => D,"
text022="            Q => Q,"
text023="            CLK => CLK);"
text024=" "
type=template
[COREGEN.VHDL Component Instantiation.PC]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component pc"
text005="    port ("
text006="    D: IN std_logic_VECTOR(15 downto 0);"
text007="    Q: OUT std_logic_VECTOR(15 downto 0);"
text008="    CLK: IN std_logic;"
text009="    CE: IN std_logic);"
text010="end component;"
text011=""
text012=""
text013=""
text014=" "
text015="-------------------------------------------------------------"
text016=" "
text017="-- The following code must appear in the VHDL architecture body."
text018="-- Substitute your own instance name and net names."
text019=" "
text020="your_instance_name : pc"
text021="        port map ("
text022="            D => D,"
text023="            Q => Q,"
text024="            CLK => CLK,"
text025="            CE => CE);"
text026=" "
type=template
[COREGEN.VHDL Component Instantiation.PROCFLAG]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component procflag"
text005="    port ("
text006="    D: IN std_logic_VECTOR(0 downto 0);"
text007="    Q: OUT std_logic_VECTOR(0 downto 0);"
text008="    CLK: IN std_logic;"
text009="    CE: IN std_logic);"
text010="end component;"
text011=""
text012=""
text013=""
text014=" "
text015="-------------------------------------------------------------"
text016=" "
text017="-- The following code must appear in the VHDL architecture body."
text018="-- Substitute your own instance name and net names."
text019=" "
text020="your_instance_name : procflag"
text021="        port map ("
text022="            D => D,"
text023="            Q => Q,"
text024="            CLK => CLK,"
text025="            CE => CE);"
text026=" "
type=template
[COREGEN.VHDL Component Instantiation.shiftmuxone]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component shiftmuxone"
text005="    port ("
text006="    MA: IN std_logic_VECTOR(15 downto 0);"
text007="    MB: IN std_logic_VECTOR(15 downto 0);"
text008="    S: IN std_logic_VECTOR(0 downto 0);"
text009="    O: OUT std_logic_VECTOR(15 downto 0));"
text010="end component;"
text011=""
text012=""
text013=""
text014=" "
text015="-------------------------------------------------------------"
text016=" "
text017="-- The following code must appear in the VHDL architecture body."
text018="-- Substitute your own instance name and net names."
text019=" "
text020="your_instance_name : shiftmuxone"
text021="        port map ("
text022="            MA => MA,"
text023="            MB => MB,"
text024="            S => S,"
text025="            O => O);"
text026=" "
type=template
[COREGEN.VHDL Component Instantiation.sixbusmux]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component sixbusmux"
text005="    port ("
text006="    MA: IN std_logic_VECTOR(15 downto 0);"
text007="    MB: IN std_logic_VECTOR(15 downto 0);"
text008="    MC: IN std_logic_VECTOR(15 downto 0);"
text009="    MD: IN std_logic_VECTOR(15 downto 0);"
text010="    ME: IN std_logic_VECTOR(15 downto 0);"
text011="    MF: IN std_logic_VECTOR(15 downto 0);"
text012="    S: IN std_logic_VECTOR(2 downto 0);"
text013="    O: OUT std_logic_VECTOR(15 downto 0));"
text014="end component;"
text015=""
text016=""
text017=""
text018=" "
text019="-------------------------------------------------------------"
text020=" "
text021="-- The following code must appear in the VHDL architecture body."
text022="-- Substitute your own instance name and net names."
text023=" "
text024="your_instance_name : sixbusmux"
text025="        port map ("
text026="            MA => MA,"
text027="            MB => MB,"
text028="            MC => MC,"
text029="            MD => MD,"
text030="            ME => ME,"
text031="            MF => MF,"
text032="            S => S,"
text033="            O => O);"
text034=" "
type=template
[COREGEN.VHDL Component Instantiation.ThreeBusMux16bit]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component threebusmux16bit"
text005="    port ("
text006="    MA: IN std_logic_VECTOR(15 downto 0);"
text007="    MB: IN std_logic_VECTOR(15 downto 0);"
text008="    MC: IN std_logic_VECTOR(15 downto 0);"
text009="    S: IN std_logic_VECTOR(1 downto 0);"
text010="    O: OUT std_logic_VECTOR(15 downto 0));"
text011="end component;"
text012=""
text013=""
text014=""
text015=" "
text016="-------------------------------------------------------------"
text017=" "
text018="-- The following code must appear in the VHDL architecture body."
text019="-- Substitute your own instance name and net names."
text020=" "
text021="your_instance_name : threebusmux16bit"
text022="        port map ("
text023="            MA => MA,"
text024="            MB => MB,"
text025="            MC => MC,"
text026="            S => S,"
text027="            O => O);"
text028=" "
type=template
[COREGEN.VHDL Component Instantiation.TwoBusMux16bit]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component twobusmux16bit"
text005="    port ("
text006="    MA: IN std_logic_VECTOR(15 downto 0);"
text007="    MB: IN std_logic_VECTOR(15 downto 0);"
text008="    S: IN std_logic_VECTOR(0 downto 0);"
text009="    O: OUT std_logic_VECTOR(15 downto 0));"
text010="end component;"
text011=""
text012=""
text013=""
text014=" "
text015="-------------------------------------------------------------"
text016=" "
text017="-- The following code must appear in the VHDL architecture body."
text018="-- Substitute your own instance name and net names."
text019=" "
text020="your_instance_name : twobusmux16bit"
text021="        port map ("
text022="            MA => MA,"
text023="            MB => MB,"
text024="            S => S,"
text025="            O => O);"
text026=" "
type=template
[COREGEN.VHDL Component Instantiation.TwoBusMux4bit]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component twobusmux4bit"
text005="    port ("
text006="    MA: IN std_logic_VECTOR(3 downto 0);"
text007="    MB: IN std_logic_VECTOR(3 downto 0);"
text008="    S: IN std_logic_VECTOR(0 downto 0);"
text009="    O: OUT std_logic_VECTOR(3 downto 0));"
text010="end component;"
text011=""
text012=""
text013=""
text014=" "
text015="-------------------------------------------------------------"
text016=" "
text017="-- The following code must appear in the VHDL architecture body."
text018="-- Substitute your own instance name and net names."
text019=" "
text020="your_instance_name : twobusmux4bit"
text021="        port map ("
text022="            MA => MA,"
text023="            MB => MB,"
text024="            S => S,"
text025="            O => O);"
text026=" "
type=template
