library verilog;
use verilog.vl_types.all;
entity bit_adder is
    port(
        a               : in     vl_logic_vector(0 downto 0);
        b               : in     vl_logic_vector(0 downto 0);
        c_in            : in     vl_logic;
        c_out           : out    vl_logic;
        s               : out    vl_logic_vector(0 downto 0)
    );
end bit_adder;
