library verilog;
use verilog.vl_types.all;
entity ofdx_mxilinx_reg1 is
    port(
        c               : in     vl_logic;
        ce              : in     vl_logic;
        d               : in     vl_logic;
        q               : out    vl_logic
    );
end ofdx_mxilinx_reg1;
