library verilog;
use verilog.vl_types.all;
entity byteram is
    generic(
        ram_a_upper     : integer := 44;
        ram_b_upper     : integer := 134;
        ram_depth       : integer := 134
    );
    port(
        writedata       : in     vl_logic_vector(15 downto 0);
        memdata         : out    vl_logic_vector(15 downto 0);
        address         : in     vl_logic_vector(15 downto 0);
        memwrite        : in     vl_logic;
        memread         : in     vl_logic;
        reset           : in     vl_logic;
        valid           : out    vl_logic;
        clk             : in     vl_logic
    );
end byteram;
