library verilog;
use verilog.vl_types.all;
entity processor is
    port(
        clk             : in     vl_logic;
        ieb             : in     vl_logic;
        inputregin      : in     vl_logic_vector(15 downto 0);
        reset           : in     vl_logic;
        wib             : in     vl_logic;
        outputregout    : out    vl_logic_vector(15 downto 0);
        valid           : out    vl_logic
    );
end processor;
