library verilog;
use verilog.vl_types.all;
entity inputreg is
    port(
        clk             : in     vl_logic;
        inputregin      : in     vl_logic_vector(15 downto 0);
        inputregwrite   : in     vl_logic;
        inputregout     : out    vl_logic_vector(15 downto 0)
    );
end inputreg;
