library verilog;
use verilog.vl_types.all;
entity concat is
    port(
        a               : in     vl_logic_vector(0 to 15);
        ir12            : in     vl_logic;
        ir114           : in     vl_logic_vector(0 to 7);
        result          : out    vl_logic_vector(0 to 15)
    );
end concat;
