library verilog;
use verilog.vl_types.all;
entity m2_1_mxilinx_alu is
    port(
        d0              : in     vl_logic;
        d1              : in     vl_logic;
        s0              : in     vl_logic;
        o               : out    vl_logic
    );
end m2_1_mxilinx_alu;
