library verilog;
use verilog.vl_types.all;
entity ctrlsta is
    port(
        aluop           : out    vl_logic_vector(1 downto 0);
        alusrca         : out    vl_logic_vector(2 downto 0);
        alusrcb         : out    vl_logic_vector(2 downto 0);
        copaddr         : out    vl_logic_vector(1 downto 0);
        ir              : in     vl_logic_vector(3 downto 0);
        memtoreg        : out    vl_logic_vector(2 downto 0);
        pcsource        : out    vl_logic_vector(1 downto 0);
        regdst          : out    vl_logic_vector(1 downto 0);
        clk             : in     vl_logic;
        interruptreturn : in     vl_logic;
        reset           : in     vl_logic;
        copwrite        : out    vl_logic;
        greater         : out    vl_logic;
        inputregwrite   : out    vl_logic;
        interruptop     : out    vl_logic;
        iord            : out    vl_logic;
        irwrite         : out    vl_logic;
        memread         : out    vl_logic;
        memwrite        : out    vl_logic;
        mfwrite         : out    vl_logic;
        outputwrite     : out    vl_logic;
        pccond          : out    vl_logic;
        pcwrite         : out    vl_logic;
        regwrite        : out    vl_logic;
        seop            : out    vl_logic
    );
end ctrlsta;
