library verilog;
use verilog.vl_types.all;
entity a is
    port(
        alusrc          : in     vl_logic_vector(2 downto 0);
        src0            : in     vl_logic_vector(15 downto 0);
        src1            : in     vl_logic_vector(15 downto 0);
        src2            : in     vl_logic_vector(15 downto 0);
        src3            : in     vl_logic_vector(15 downto 0);
        src4            : in     vl_logic_vector(15 downto 0);
        src5            : in     vl_logic_vector(15 downto 0);
        src6            : in     vl_logic_vector(15 downto 0);
        rout            : out    vl_logic_vector(15 downto 0)
    );
end a;
