library verilog;
use verilog.vl_types.all;
entity adder is
    port(
        a               : in     vl_logic_vector(0 downto 0);
        b               : in     vl_logic_vector(0 downto 0);
        c_in            : in     vl_logic;
        q_c_out         : out    vl_logic;
        q               : out    vl_logic_vector(0 downto 0);
        clk             : in     vl_logic
    );
end adder;
