library verilog;
use verilog.vl_types.all;
entity outputreg is
    port(
        clk             : in     vl_logic;
        outputregin     : in     vl_logic_vector(15 downto 0);
        outputregwrite  : in     vl_logic;
        outputregout    : out    vl_logic_vector(15 downto 0)
    );
end outputreg;
