library verilog;
use verilog.vl_types.all;
entity ir is
    port(
        clk             : in     vl_logic;
        irin            : in     vl_logic_vector(15 downto 0);
        irwrite         : in     vl_logic;
        irout           : out    vl_logic_vector(15 downto 0)
    );
end ir;
