library verilog;
use verilog.vl_types.all;
entity fourbitmux_2input is
    port(
        in0             : in     vl_logic_vector(3 downto 0);
        in1             : in     vl_logic_vector(3 downto 0);
        source          : in     vl_logic;
        r               : out    vl_logic_vector(3 downto 0)
    );
end fourbitmux_2input;
