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// The synopsys directives "translate_off/translate_on" specified below are
// supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).

// You must compile the wrapper file adder.v when simulating
// the core, adder. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Guide".

module adder (
	A,
	B,
	C_IN,
	Q_C_OUT,
	Q,
	CLK);    // synthesis black_box

input [0 : 0] A;
input [0 : 0] B;
input C_IN;
output Q_C_OUT;
output [0 : 0] Q;
input CLK;

// synopsys translate_off

	C_ADDSUB_V6_0 #(
		0,	// c_add_mode
		"0",	// c_ainit_val
		1,	// c_a_type
		1,	// c_a_width
		0,	// c_bypass_enable
		0,	// c_bypass_low
		0,	// c_b_constant
		1,	// c_b_type
		"0",	// c_b_value
		1,	// c_b_width
		1,	// c_enable_rlocs
		0,	// c_has_aclr
		0,	// c_has_add
		0,	// c_has_ainit
		0,	// c_has_aset
		0,	// c_has_a_signed
		0,	// c_has_bypass
		0,	// c_has_bypass_with_cin
		0,	// c_has_b_in
		0,	// c_has_b_out
		0,	// c_has_b_signed
		0,	// c_has_ce
		1,	// c_has_c_in
		0,	// c_has_c_out
		0,	// c_has_ovfl
		1,	// c_has_q
		0,	// c_has_q_b_out
		1,	// c_has_q_c_out
		0,	// c_has_q_ovfl
		0,	// c_has_s
		0,	// c_has_sclr
		0,	// c_has_sinit
		0,	// c_has_sset
		0,	// c_high_bit
		1,	// c_latency
		0,	// c_low_bit
		1,	// c_out_width
		1,	// c_pipe_stages
		"0",	// c_sinit_val
		0,	// c_sync_enable
		1)	// c_sync_priority
	inst (
		.A(A),
		.B(B),
		.C_IN(C_IN),
		.Q_C_OUT(Q_C_OUT),
		.Q(Q),
		.CLK(CLK),
		.ACLR(),
		.ADD(),
		.AINIT(),
		.ASET(),
		.A_SIGNED(),
		.B_OUT(),
		.B_SIGNED(),
		.C_OUT(),
		.B_IN(),
		.BYPASS(),
		.CE(),
		.OVFL(),
		.Q_B_OUT(),
		.Q_OVFL(),
		.S(),
		.SCLR(),
		.SINIT(),
		.SSET());


// synopsys translate_on

// FPGA Express black box declaration
// synopsys attribute fpga_dont_touch "true"
// synthesis attribute fpga_dont_touch of adder is "true"

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of adder is "black_box"

endmodule

