library verilog;
use verilog.vl_types.all;
entity aluout is
    port(
        aluoutin        : in     vl_logic_vector(15 downto 0);
        clk             : in     vl_logic;
        write           : in     vl_logic;
        aluoutout       : out    vl_logic_vector(15 downto 0)
    );
end aluout;
