library verilog;
use verilog.vl_types.all;
entity pcsourcemux is
    port(
        con             : in     vl_logic_vector(1 downto 0);
        src0            : in     vl_logic_vector(15 downto 0);
        src1            : in     vl_logic_vector(15 downto 0);
        src2            : in     vl_logic_vector(15 downto 0);
        result          : out    vl_logic_vector(15 downto 0)
    );
end pcsourcemux;
