// C:\XILINX\PROJECTS\ALU
// Verilog Test fixture created by
// HDL Bencher 6.1i
// Thu Feb 19 20:11:01 2004
// 
// Notes:
// 1) This test fixture has been automatically generated from
//   your Test Bench Waveform
// 2) To use this as a user modifiable test fixture do the following:
//   - Save it as a file with a .tf extension (i.e. File->Save As...)
//   - Add it to your project as a testbench source (i.e. Project->Add Source...)
// 

`timescale 1ns/1ns

`define ADDR_SZ	3
`define RAM_B_LOWER	20
`define RAM_WIDTH	16
`define RAM_A_UPPER	10
`define RAM_C_LOWER	40
`define RAM_C_UPPER	50
`define RAM_B_UPPER	30
`define RAM_A_SZ	32
`define RAM_A_LOWER	0
`define RAM_B_SZ	32
`define REG_WIDTH	16

module aluouttest;
	reg [15:0] ALUOutin;
	reg CLK;
	reg Write;
	wire [15:0] ALUOutout;

	aluout UUT (
		.ALUOutin(ALUOutin),
		.CLK(CLK),
		.Write(Write),
		.ALUOutout(ALUOutout)
	);

	integer TX_FILE;
	integer TX_ERROR;

always
begin 			//clock process
	CLK = 1'b0;
	#10
	CLK = 1'b1;
	#10
	#40
	CLK = 1'b0;
	#40
	CLK = 1'b0;
end

initial
begin
	TX_ERROR=0;
	TX_FILE=$fopen("results.txt");

	// --------------------
	ALUOutin = 16'b0000000000000000; //0
	Write = 1'b0;
	// --------------------
	#100 // Time=100 ns
	// --------------------

	if (TX_ERROR == 0) begin
		$display("No errors or warnings");
		$fdisplay(TX_FILE,"No errors or warnings");
	end else begin
		$display("%d errors found in simulation",TX_ERROR);
		$fdisplay(TX_FILE,"%d errors found in simulation",TX_ERROR);
	end

	$fclose(TX_FILE);
	$stop;

end

task CHECK_ALUOutout;
	input [15:0] NEXT_ALUOutout;

	#0 begin
		if (NEXT_ALUOutout !== ALUOutout) begin
			$display("Error at time=%dns ALUOutout=%b, expected=%b",
				$time, ALUOutout, NEXT_ALUOutout);
			$fdisplay(TX_FILE,"Error at time=%dns ALUOutout=%b, expected=%b",
				$time, ALUOutout, NEXT_ALUOutout);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

endmodule
