library verilog;
use verilog.vl_types.all;
entity and16_mxilinx_alufull is
    port(
        i0              : in     vl_logic;
        i1              : in     vl_logic;
        i2              : in     vl_logic;
        i3              : in     vl_logic;
        i4              : in     vl_logic;
        i5              : in     vl_logic;
        i6              : in     vl_logic;
        i7              : in     vl_logic;
        i8              : in     vl_logic;
        i9              : in     vl_logic;
        i10             : in     vl_logic;
        i11             : in     vl_logic;
        i12             : in     vl_logic;
        i13             : in     vl_logic;
        i14             : in     vl_logic;
        i15             : in     vl_logic;
        o               : out    vl_logic
    );
end and16_mxilinx_alufull;
