library verilog;
use verilog.vl_types.all;
entity regs is
    port(
        clk             : in     vl_logic;
        regin           : in     vl_logic_vector(15 downto 0);
        write           : in     vl_logic;
        regout          : out    vl_logic_vector(15 downto 0)
    );
end regs;
