library verilog;
use verilog.vl_types.all;
entity shiftleftlogical is
    port(
        shiftby         : in     vl_logic_vector(8 downto 0);
        shiftdata       : in     vl_logic_vector(15 downto 0);
        shifteddata     : out    vl_logic_vector(15 downto 0)
    );
end shiftleftlogical;
