## NOTE:  Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Wed Feb 18 18:45:15 US Eastern Standard Time 2004
##
vlib work
vlog  RegFile.v
vlog  regfile_tb.tfw
vlog  "C:/Xilinx/verilog/src/glbl.v"
vsim -t 1ps  -L xilinxcorelib_ver -L unisims_ver  -lib work regfile_tb glbl
do regfile_tb.udo
view wave
add wave *
view structure
view signals
run -all
