library verilog;
use verilog.vl_types.all;
entity alufull is
    port(
        a               : in     vl_logic_vector(15 downto 0);
        b               : in     vl_logic_vector(15 downto 0);
        clk             : in     vl_logic;
        operator        : in     vl_logic_vector(1 downto 0);
        r               : out    vl_logic_vector(15 downto 0);
        zero            : out    vl_logic
    );
end alufull;
