[COREGEN.VERILOG Component Instantiation.Adder]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="adder YourInstanceName ("
text007="    .A(A),"
text008="    .B(B),"
text009="    .C_IN(C_IN),"
text010="    .Q_C_OUT(Q_C_OUT),"
text011="    .Q(Q),"
text012="    .CLK(CLK));"
text013=""
text014=" "
type=template
[COREGEN.VERILOG Component Instantiation.mux16_1_1]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="mux16_1_1 YourInstanceName ("
text007="    .MA(MA),"
text008="    .MB(MB),"
text009="    .MC(MC),"
text010="    .MD(MD),"
text011="    .ME(ME),"
text012="    .MF(MF),"
text013="    .MG(MG),"
text014="    .MH(MH),"
text015="    .MAA(MAA),"
text016="    .MAB(MAB),"
text017="    .MAC(MAC),"
text018="    .MAD(MAD),"
text019="    .MAE(MAE),"
text020="    .MAF(MAF),"
text021="    .MAG(MAG),"
text022="    .MAH(MAH),"
text023="    .S(S),"
text024="    .Q(Q),"
text025="    .CLK(CLK));"
text026=""
text027=" "
type=template
[COREGEN.VERILOG Component Instantiation.mux2_16_1]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="mux2_16_1 YourInstanceName ("
text007="    .MA(MA),"
text008="    .MB(MB),"
text009="    .S(S),"
text010="    .Q(Q),"
text011="    .CLK(CLK));"
text012=""
text013=" "
type=template
[COREGEN.VERILOG Component Instantiation.mux3_3_1]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="mux3_3_1 YourInstanceName ("
text007="    .MA(MA),"
text008="    .MB(MB),"
text009="    .MC(MC),"
text010="    .S(S),"
text011="    .Q(Q),"
text012="    .CLK(CLK));"
text013=""
text014=" "
type=template
[COREGEN.VERILOG Component Instantiation.mux4_1]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="mux4_1 YourInstanceName ("
text007="    .M(M),"
text008="    .S(S),"
text009="    .Q(Q),"
text010="    .CLK(CLK));"
text011=""
text012=" "
type=template
[COREGEN.VERILOG Component Instantiation.mux4_16_1]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="mux4_16_1 YourInstanceName ("
text007="    .MA(MA),"
text008="    .MB(MB),"
text009="    .MC(MC),"
text010="    .MD(MD),"
text011="    .S(S),"
text012="    .O(O));"
text013=""
text014=" "
type=template
[COREGEN.VERILOG Component Instantiation.mux5_16_1]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="mux5_16_1 YourInstanceName ("
text007="    .MA(MA),"
text008="    .MB(MB),"
text009="    .MC(MC),"
text010="    .MD(MD),"
text011="    .ME(ME),"
text012="    .S(S),"
text013="    .Q(Q),"
text014="    .CLK(CLK));"
text015=""
text016=" "
type=template
[COREGEN.VERILOG Component Instantiation.mux6_16_1]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="mux6_16_1 YourInstanceName ("
text007="    .MA(MA),"
text008="    .MB(MB),"
text009="    .MC(MC),"
text010="    .MD(MD),"
text011="    .ME(ME),"
text012="    .MF(MF),"
text013="    .S(S),"
text014="    .Q(Q),"
text015="    .CLK(CLK));"
text016=""
text017=" "
type=template
[COREGEN.VERILOG Component Instantiation.mux8_16_1]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="mux8_16_1 YourInstanceName ("
text007="    .MA(MA),"
text008="    .MB(MB),"
text009="    .MC(MC),"
text010="    .MD(MD),"
text011="    .ME(ME),"
text012="    .MF(MF),"
text013="    .MG(MG),"
text014="    .MH(MH),"
text015="    .S(S),"
text016="    .O(O));"
text017=""
text018=" "
type=template
[COREGEN.VERILOG Component Instantiation.mux_3_1]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="mux_3_1 YourInstanceName ("
text007="    .MA(MA),"
text008="    .MB(MB),"
text009="    .MC(MC),"
text010="    .S(S),"
text011="    .Q(Q),"
text012="    .CLK(CLK));"
text013=""
text014=" "
type=template
[COREGEN.VERILOG Component Instantiation.slll]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="slll YourInstanceName ("
text007="    .MA(MA),"
text008="    .MB(MB),"
text009="    .MC(MC),"
text010="    .MD(MD),"
text011="    .ME(ME),"
text012="    .MF(MF),"
text013="    .MG(MG),"
text014="    .MH(MH),"
text015="    .MAA(MAA),"
text016="    .MAB(MAB),"
text017="    .MAC(MAC),"
text018="    .MAD(MAD),"
text019="    .MAE(MAE),"
text020="    .MAF(MAF),"
text021="    .MAG(MAG),"
text022="    .MAH(MAH),"
text023="    .S(S),"
text024="    .O(O));"
text025=""
text026=" "
type=template
[COREGEN.VHDL Component Instantiation.Adder]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component adder"
text005="    port ("
text006="    A: IN std_logic_VECTOR(0 downto 0);"
text007="    B: IN std_logic_VECTOR(0 downto 0);"
text008="    C_IN: IN std_logic;"
text009="    Q_C_OUT: OUT std_logic;"
text010="    Q: OUT std_logic_VECTOR(0 downto 0);"
text011="    CLK: IN std_logic);"
text012="end component;"
text013=""
text014=""
text015=""
text016=" "
text017="-------------------------------------------------------------"
text018=" "
text019="-- The following code must appear in the VHDL architecture body."
text020="-- Substitute your own instance name and net names."
text021=" "
text022="your_instance_name : adder"
text023="        port map ("
text024="            A => A,"
text025="            B => B,"
text026="            C_IN => C_IN,"
text027="            Q_C_OUT => Q_C_OUT,"
text028="            Q => Q,"
text029="            CLK => CLK);"
text030=" "
type=template
[COREGEN.VHDL Component Instantiation.mux16_1_1]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component mux16_1_1"
text005="    port ("
text006="    MA: IN std_logic_VECTOR(0 downto 0);"
text007="    MB: IN std_logic_VECTOR(0 downto 0);"
text008="    MC: IN std_logic_VECTOR(0 downto 0);"
text009="    MD: IN std_logic_VECTOR(0 downto 0);"
text010="    ME: IN std_logic_VECTOR(0 downto 0);"
text011="    MF: IN std_logic_VECTOR(0 downto 0);"
text012="    MG: IN std_logic_VECTOR(0 downto 0);"
text013="    MH: IN std_logic_VECTOR(0 downto 0);"
text014="    MAA: IN std_logic_VECTOR(0 downto 0);"
text015="    MAB: IN std_logic_VECTOR(0 downto 0);"
text016="    MAC: IN std_logic_VECTOR(0 downto 0);"
text017="    MAD: IN std_logic_VECTOR(0 downto 0);"
text018="    MAE: IN std_logic_VECTOR(0 downto 0);"
text019="    MAF: IN std_logic_VECTOR(0 downto 0);"
text020="    MAG: IN std_logic_VECTOR(0 downto 0);"
text021="    MAH: IN std_logic_VECTOR(0 downto 0);"
text022="    S: IN std_logic_VECTOR(3 downto 0);"
text023="    Q: OUT std_logic_VECTOR(0 downto 0);"
text024="    CLK: IN std_logic);"
text025="end component;"
text026=""
text027=""
text028=""
text029=" "
text030="-------------------------------------------------------------"
text031=" "
text032="-- The following code must appear in the VHDL architecture body."
text033="-- Substitute your own instance name and net names."
text034=" "
text035="your_instance_name : mux16_1_1"
text036="        port map ("
text037="            MA => MA,"
text038="            MB => MB,"
text039="            MC => MC,"
text040="            MD => MD,"
text041="            ME => ME,"
text042="            MF => MF,"
text043="            MG => MG,"
text044="            MH => MH,"
text045="            MAA => MAA,"
text046="            MAB => MAB,"
text047="            MAC => MAC,"
text048="            MAD => MAD,"
text049="            MAE => MAE,"
text050="            MAF => MAF,"
text051="            MAG => MAG,"
text052="            MAH => MAH,"
text053="            S => S,"
text054="            Q => Q,"
text055="            CLK => CLK);"
text056=" "
type=template
[COREGEN.VHDL Component Instantiation.mux2_16_1]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component mux2_16_1"
text005="    port ("
text006="    MA: IN std_logic_VECTOR(15 downto 0);"
text007="    MB: IN std_logic_VECTOR(15 downto 0);"
text008="    S: IN std_logic_VECTOR(0 downto 0);"
text009="    Q: OUT std_logic_VECTOR(15 downto 0);"
text010="    CLK: IN std_logic);"
text011="end component;"
text012=""
text013=""
text014=""
text015=" "
text016="-------------------------------------------------------------"
text017=" "
text018="-- The following code must appear in the VHDL architecture body."
text019="-- Substitute your own instance name and net names."
text020=" "
text021="your_instance_name : mux2_16_1"
text022="        port map ("
text023="            MA => MA,"
text024="            MB => MB,"
text025="            S => S,"
text026="            Q => Q,"
text027="            CLK => CLK);"
text028=" "
type=template
[COREGEN.VHDL Component Instantiation.mux3_3_1]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component mux3_3_1"
text005="    port ("
text006="    MA: IN std_logic_VECTOR(2 downto 0);"
text007="    MB: IN std_logic_VECTOR(2 downto 0);"
text008="    MC: IN std_logic_VECTOR(2 downto 0);"
text009="    S: IN std_logic_VECTOR(1 downto 0);"
text010="    Q: OUT std_logic_VECTOR(2 downto 0);"
text011="    CLK: IN std_logic);"
text012="end component;"
text013=""
text014=""
text015=""
text016=" "
text017="-------------------------------------------------------------"
text018=" "
text019="-- The following code must appear in the VHDL architecture body."
text020="-- Substitute your own instance name and net names."
text021=" "
text022="your_instance_name : mux3_3_1"
text023="        port map ("
text024="            MA => MA,"
text025="            MB => MB,"
text026="            MC => MC,"
text027="            S => S,"
text028="            Q => Q,"
text029="            CLK => CLK);"
text030=" "
type=template
[COREGEN.VHDL Component Instantiation.mux4_1]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component mux4_1"
text005="    port ("
text006="    M: IN std_logic_VECTOR(3 downto 0);"
text007="    S: IN std_logic_VECTOR(1 downto 0);"
text008="    Q: OUT std_logic;"
text009="    CLK: IN std_logic);"
text010="end component;"
text011=""
text012=""
text013=""
text014=" "
text015="-------------------------------------------------------------"
text016=" "
text017="-- The following code must appear in the VHDL architecture body."
text018="-- Substitute your own instance name and net names."
text019=" "
text020="your_instance_name : mux4_1"
text021="        port map ("
text022="            M => M,"
text023="            S => S,"
text024="            Q => Q,"
text025="            CLK => CLK);"
text026=" "
type=template
[COREGEN.VHDL Component Instantiation.mux4_16_1]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component mux4_16_1"
text005="    port ("
text006="    MA: IN std_logic_VECTOR(15 downto 0);"
text007="    MB: IN std_logic_VECTOR(15 downto 0);"
text008="    MC: IN std_logic_VECTOR(15 downto 0);"
text009="    MD: IN std_logic_VECTOR(15 downto 0);"
text010="    S: IN std_logic_VECTOR(1 downto 0);"
text011="    O: OUT std_logic_VECTOR(15 downto 0));"
text012="end component;"
text013=""
text014=""
text015=""
text016=" "
text017="-------------------------------------------------------------"
text018=" "
text019="-- The following code must appear in the VHDL architecture body."
text020="-- Substitute your own instance name and net names."
text021=" "
text022="your_instance_name : mux4_16_1"
text023="        port map ("
text024="            MA => MA,"
text025="            MB => MB,"
text026="            MC => MC,"
text027="            MD => MD,"
text028="            S => S,"
text029="            O => O);"
text030=" "
type=template
[COREGEN.VHDL Component Instantiation.mux5_16_1]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component mux5_16_1"
text005="    port ("
text006="    MA: IN std_logic_VECTOR(15 downto 0);"
text007="    MB: IN std_logic_VECTOR(15 downto 0);"
text008="    MC: IN std_logic_VECTOR(15 downto 0);"
text009="    MD: IN std_logic_VECTOR(15 downto 0);"
text010="    ME: IN std_logic_VECTOR(15 downto 0);"
text011="    S: IN std_logic_VECTOR(2 downto 0);"
text012="    Q: OUT std_logic_VECTOR(15 downto 0);"
text013="    CLK: IN std_logic);"
text014="end component;"
text015=""
text016=""
text017=""
text018=" "
text019="-------------------------------------------------------------"
text020=" "
text021="-- The following code must appear in the VHDL architecture body."
text022="-- Substitute your own instance name and net names."
text023=" "
text024="your_instance_name : mux5_16_1"
text025="        port map ("
text026="            MA => MA,"
text027="            MB => MB,"
text028="            MC => MC,"
text029="            MD => MD,"
text030="            ME => ME,"
text031="            S => S,"
text032="            Q => Q,"
text033="            CLK => CLK);"
text034=" "
type=template
[COREGEN.VHDL Component Instantiation.mux6_16_1]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component mux6_16_1"
text005="    port ("
text006="    MA: IN std_logic_VECTOR(15 downto 0);"
text007="    MB: IN std_logic_VECTOR(15 downto 0);"
text008="    MC: IN std_logic_VECTOR(15 downto 0);"
text009="    MD: IN std_logic_VECTOR(15 downto 0);"
text010="    ME: IN std_logic_VECTOR(15 downto 0);"
text011="    MF: IN std_logic_VECTOR(15 downto 0);"
text012="    S: IN std_logic_VECTOR(2 downto 0);"
text013="    Q: OUT std_logic_VECTOR(15 downto 0);"
text014="    CLK: IN std_logic);"
text015="end component;"
text016=""
text017=""
text018=""
text019=" "
text020="-------------------------------------------------------------"
text021=" "
text022="-- The following code must appear in the VHDL architecture body."
text023="-- Substitute your own instance name and net names."
text024=" "
text025="your_instance_name : mux6_16_1"
text026="        port map ("
text027="            MA => MA,"
text028="            MB => MB,"
text029="            MC => MC,"
text030="            MD => MD,"
text031="            ME => ME,"
text032="            MF => MF,"
text033="            S => S,"
text034="            Q => Q,"
text035="            CLK => CLK);"
text036=" "
type=template
[COREGEN.VHDL Component Instantiation.mux8_16_1]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component mux8_16_1"
text005="    port ("
text006="    MA: IN std_logic_VECTOR(15 downto 0);"
text007="    MB: IN std_logic_VECTOR(15 downto 0);"
text008="    MC: IN std_logic_VECTOR(15 downto 0);"
text009="    MD: IN std_logic_VECTOR(15 downto 0);"
text010="    ME: IN std_logic_VECTOR(15 downto 0);"
text011="    MF: IN std_logic_VECTOR(15 downto 0);"
text012="    MG: IN std_logic_VECTOR(15 downto 0);"
text013="    MH: IN std_logic_VECTOR(15 downto 0);"
text014="    S: IN std_logic_VECTOR(2 downto 0);"
text015="    O: OUT std_logic_VECTOR(15 downto 0));"
text016="end component;"
text017=""
text018=""
text019=""
text020=" "
text021="-------------------------------------------------------------"
text022=" "
text023="-- The following code must appear in the VHDL architecture body."
text024="-- Substitute your own instance name and net names."
text025=" "
text026="your_instance_name : mux8_16_1"
text027="        port map ("
text028="            MA => MA,"
text029="            MB => MB,"
text030="            MC => MC,"
text031="            MD => MD,"
text032="            ME => ME,"
text033="            MF => MF,"
text034="            MG => MG,"
text035="            MH => MH,"
text036="            S => S,"
text037="            O => O);"
text038=" "
type=template
[COREGEN.VHDL Component Instantiation.mux_3_1]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component mux_3_1"
text005="    port ("
text006="    MA: IN std_logic_VECTOR(15 downto 0);"
text007="    MB: IN std_logic_VECTOR(15 downto 0);"
text008="    MC: IN std_logic_VECTOR(15 downto 0);"
text009="    S: IN std_logic_VECTOR(1 downto 0);"
text010="    Q: OUT std_logic_VECTOR(15 downto 0);"
text011="    CLK: IN std_logic);"
text012="end component;"
text013=""
text014=""
text015=""
text016=" "
text017="-------------------------------------------------------------"
text018=" "
text019="-- The following code must appear in the VHDL architecture body."
text020="-- Substitute your own instance name and net names."
text021=" "
text022="your_instance_name : mux_3_1"
text023="        port map ("
text024="            MA => MA,"
text025="            MB => MB,"
text026="            MC => MC,"
text027="            S => S,"
text028="            Q => Q,"
text029="            CLK => CLK);"
text030=" "
type=template
[COREGEN.VHDL Component Instantiation.slll]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component slll"
text005="    port ("
text006="    MA: IN std_logic_VECTOR(15 downto 0);"
text007="    MB: IN std_logic_VECTOR(15 downto 0);"
text008="    MC: IN std_logic_VECTOR(15 downto 0);"
text009="    MD: IN std_logic_VECTOR(15 downto 0);"
text010="    ME: IN std_logic_VECTOR(15 downto 0);"
text011="    MF: IN std_logic_VECTOR(15 downto 0);"
text012="    MG: IN std_logic_VECTOR(15 downto 0);"
text013="    MH: IN std_logic_VECTOR(15 downto 0);"
text014="    MAA: IN std_logic_VECTOR(15 downto 0);"
text015="    MAB: IN std_logic_VECTOR(15 downto 0);"
text016="    MAC: IN std_logic_VECTOR(15 downto 0);"
text017="    MAD: IN std_logic_VECTOR(15 downto 0);"
text018="    MAE: IN std_logic_VECTOR(15 downto 0);"
text019="    MAF: IN std_logic_VECTOR(15 downto 0);"
text020="    MAG: IN std_logic_VECTOR(15 downto 0);"
text021="    MAH: IN std_logic_VECTOR(15 downto 0);"
text022="    S: IN std_logic_VECTOR(3 downto 0);"
text023="    O: OUT std_logic_VECTOR(15 downto 0));"
text024="end component;"
text025=""
text026=""
text027=""
text028=" "
text029="-------------------------------------------------------------"
text030=" "
text031="-- The following code must appear in the VHDL architecture body."
text032="-- Substitute your own instance name and net names."
text033=" "
text034="your_instance_name : slll"
text035="        port map ("
text036="            MA => MA,"
text037="            MB => MB,"
text038="            MC => MC,"
text039="            MD => MD,"
text040="            ME => ME,"
text041="            MF => MF,"
text042="            MG => MG,"
text043="            MH => MH,"
text044="            MAA => MAA,"
text045="            MAB => MAB,"
text046="            MAC => MAC,"
text047="            MAD => MAD,"
text048="            MAE => MAE,"
text049="            MAF => MAF,"
text050="            MAG => MAG,"
text051="            MAH => MAH,"
text052="            S => S,"
text053="            O => O);"
text054=" "
type=template
