library verilog;
use verilog.vl_types.all;
entity alu is
    port(
        a               : in     vl_logic;
        b               : in     vl_logic;
        binv            : in     vl_logic;
        cin             : in     vl_logic;
        clk             : in     vl_logic;
        operator        : in     vl_logic;
        cout            : out    vl_logic;
        r               : out    vl_logic
    );
end alu;
