library verilog;
use verilog.vl_types.all;
entity mux5_16_1 is
    port(
        ma              : in     vl_logic_vector(15 downto 0);
        mb              : in     vl_logic_vector(15 downto 0);
        mc              : in     vl_logic_vector(15 downto 0);
        md              : in     vl_logic_vector(15 downto 0);
        me              : in     vl_logic_vector(15 downto 0);
        s               : in     vl_logic_vector(2 downto 0);
        q               : out    vl_logic_vector(15 downto 0);
        clk             : in     vl_logic
    );
end mux5_16_1;
