library verilog;
use verilog.vl_types.all;
entity mf is
    port(
        clk             : in     vl_logic;
        mfin            : in     vl_logic_vector(15 downto 0);
        mfwrite         : in     vl_logic;
        mfout           : out    vl_logic_vector(15 downto 0)
    );
end mf;
