library verilog;
use verilog.vl_types.all;
entity mux_16bit_2input is
    port(
        in_0            : in     vl_logic_vector(15 downto 0);
        in_1            : in     vl_logic_vector(15 downto 0);
        source          : in     vl_logic;
        r               : out    vl_logic_vector(15 downto 0)
    );
end mux_16bit_2input;
