library verilog;
use verilog.vl_types.all;
entity cop is
    port(
        addr1write      : in     vl_logic;
        addr2write      : in     vl_logic;
        clk             : in     vl_logic;
        copaddr         : in     vl_logic_vector(1 downto 0);
        copwrite        : in     vl_logic;
        pcin            : in     vl_logic_vector(15 downto 0);
        copout          : out    vl_logic_vector(15 downto 0)
    );
end cop;
