library verilog;
use verilog.vl_types.all;
entity shell_ctrlsta is
    port(
        clk             : in     vl_logic;
        interruptreturn : in     vl_logic;
        ir12            : in     vl_logic;
        ir13            : in     vl_logic;
        ir14            : in     vl_logic;
        ir15            : in     vl_logic;
        reset           : in     vl_logic;
        aluop0          : out    vl_logic;
        aluop1          : out    vl_logic;
        alusrca0        : out    vl_logic;
        alusrca1        : out    vl_logic;
        alusrca2        : out    vl_logic;
        alusrcb0        : out    vl_logic;
        alusrcb1        : out    vl_logic;
        alusrcb2        : out    vl_logic;
        copaddr0        : out    vl_logic;
        copaddr1        : out    vl_logic;
        copwrite        : out    vl_logic;
        greater         : out    vl_logic;
        inputregwrite   : out    vl_logic;
        interruptop     : out    vl_logic;
        iord            : out    vl_logic;
        irwrite         : out    vl_logic;
        memread         : out    vl_logic;
        memtoreg0       : out    vl_logic;
        memtoreg1       : out    vl_logic;
        memtoreg2       : out    vl_logic;
        memwrite        : out    vl_logic;
        mfwrite         : out    vl_logic;
        outputwrite     : out    vl_logic;
        pccond          : out    vl_logic;
        pcsource0       : out    vl_logic;
        pcsource1       : out    vl_logic;
        pcwrite         : out    vl_logic;
        regdst0         : out    vl_logic;
        regdst1         : out    vl_logic;
        regwrite        : out    vl_logic;
        seop            : out    vl_logic
    );
end shell_ctrlsta;
