library verilog;
use verilog.vl_types.all;
entity regfile is
    generic(
        num_regs        : integer := 8
    );
    port(
        readreg1        : in     vl_logic_vector(2 downto 0);
        readreg2        : in     vl_logic_vector(2 downto 0);
        writereg        : in     vl_logic_vector(2 downto 0);
        writedata       : in     vl_logic_vector(15 downto 0);
        regwrite        : in     vl_logic;
        readdata1       : out    vl_logic_vector(15 downto 0);
        readdata2       : out    vl_logic_vector(15 downto 0);
        clk             : in     vl_logic
    );
end regfile;
