library verilog;
use verilog.vl_types.all;
entity aluandaluouttest is
    port(
        aluop           : in     vl_logic_vector(1 downto 0);
        aout            : in     vl_logic_vector(15 downto 0);
        b               : in     vl_logic_vector(15 downto 0);
        clock           : in     vl_logic;
        reset           : in     vl_logic;
        aluout          : out    vl_logic_vector(15 downto 0);
        zeroout         : out    vl_logic
    );
end aluandaluouttest;
