library verilog;
use verilog.vl_types.all;
entity mux4b is
    port(
        mux_out         : out    vl_logic_vector(3 downto 0);
        data0           : in     vl_logic_vector(3 downto 0);
        data1           : in     vl_logic_vector(3 downto 0);
        data2           : in     vl_logic_vector(3 downto 0);
        data3           : in     vl_logic_vector(3 downto 0);
        controlin       : in     vl_logic_vector(1 downto 0)
    );
end mux4b;
