// C:\XILINX\CSSE\MAINDATAPATH
// Verilog Annotation Test Bench created by
// HDL Bencher 6.1i
// Fri Feb 13 20:07:14 2004

`timescale 1ns/1ns

module se1Test;
	reg [3:0] Q;
	wire [15:0] D;

	se1 UUT (
		.Q(Q),
		.D(D)
	);

	integer TX_FILE;
	integer TX_ERROR;

always begin // Annotate outputs process
	#50
	ANNOTATE_D;
	#50
	 begin end //null command
end

initial
begin
	TX_ERROR=0;
	TX_FILE=$fopen("c:\\xilinx\\csse\\maindatapath\\se1test.ano");

	// --------------------
	Q = 4'b0000; //0
	// --------------------
	#100 // Time=100 ns
	Q = 4'b1111; //F
	// --------------------
	#100 // Time=200 ns
	Q = 4'b0011; //3
	// --------------------
	#100 // Time=300 ns
	Q = 4'b1100; //C
	// --------------------
	#150 // Time=450 ns
	// --------------------

	begin
		$display("Success! Annotation Simulation Complete.");
		$fdisplay(TX_FILE,"Total[%d]",TX_ERROR);
	end

	$fclose(TX_FILE);
	$stop;

end

task ANNOTATE_D;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,D,%b]",
			$time, D);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

endmodule
