library verilog;
use verilog.vl_types.all;
entity shell_control is
    port(
        clk             : in     vl_logic;
        ctrlinterrupt   : in     vl_logic;
        ir0             : in     vl_logic;
        ir1             : in     vl_logic;
        ir2             : in     vl_logic;
        ir3             : in     vl_logic;
        ir4             : in     vl_logic;
        ir5             : in     vl_logic;
        ir6             : in     vl_logic;
        ir7             : in     vl_logic;
        ir8             : in     vl_logic;
        ir9             : in     vl_logic;
        ir10            : in     vl_logic;
        ir11            : in     vl_logic;
        ir12            : in     vl_logic;
        ir13            : in     vl_logic;
        ir14            : in     vl_logic;
        ir15            : in     vl_logic;
        reset           : in     vl_logic;
        aluop0          : out    vl_logic;
        aluop1          : out    vl_logic;
        alusrcb0        : out    vl_logic;
        alusrcb1        : out    vl_logic;
        check           : out    vl_logic;
        epcwrite        : out    vl_logic;
        iebclear        : out    vl_logic;
        iebcontrol      : out    vl_logic;
        iord            : out    vl_logic;
        irwrite         : out    vl_logic;
        memread         : out    vl_logic;
        memtoreg0       : out    vl_logic;
        memtoreg1       : out    vl_logic;
        memtoreg2       : out    vl_logic;
        memwrite        : out    vl_logic;
        pcsource0       : out    vl_logic;
        pcsource1       : out    vl_logic;
        pcsource2       : out    vl_logic;
        pcwrite         : out    vl_logic;
        pcwritecond     : out    vl_logic;
        portwrite       : out    vl_logic;
        regbcontrol     : out    vl_logic;
        regdst0         : out    vl_logic;
        regdst1         : out    vl_logic;
        regwrite        : out    vl_logic;
        secontrol       : out    vl_logic
    );
end shell_control;
