library verilog;
use verilog.vl_types.all;
entity fd4ce_mxilinx_irq is
    port(
        c               : in     vl_logic;
        ce              : in     vl_logic;
        clr             : in     vl_logic;
        d0              : in     vl_logic;
        d1              : in     vl_logic;
        d2              : in     vl_logic;
        d3              : in     vl_logic;
        q0              : out    vl_logic;
        q1              : out    vl_logic;
        q2              : out    vl_logic;
        q3              : out    vl_logic
    );
end fd4ce_mxilinx_irq;
