library verilog;
use verilog.vl_types.all;
entity shifter is
    port(
        linein          : in     vl_logic_vector(15 downto 0);
        lineout         : out    vl_logic_vector(15 downto 0);
        clock           : in     vl_logic;
        controlin       : in     vl_logic_vector(3 downto 0)
    );
end shifter;
