library verilog;
use verilog.vl_types.all;
entity mdr is
    port(
        clear           : in     vl_logic;
        clock           : in     vl_logic;
        clockenable     : in     vl_logic;
        input           : in     vl_logic_vector(15 downto 0);
        output          : out    vl_logic_vector(15 downto 0)
    );
end mdr;
