module PortFile(
   PortAddr,
   WritePort,
   PortData,
   PortWrite,
   PortOut,               
   CLK);

// Definitions

parameter NUM_REGS = 4;
`define ADDR_SZ 2
`define REG_WIDTH 16

// Inputs

input [`ADDR_SZ-1:0] PortAddr;
input [`ADDR_SZ-1:0] WritePort;
input [`REG_WIDTH-1:0] PortOut;
input PortWrite;
input CLK;

// Outputs

output [`REG_WIDTH-1:0] PortData;

// Signals

wire [`REG_WIDTH-1:0] PortData;

// The registers

reg [`REG_WIDTH-1:0] Reg [NUM_REGS-1:0];

assign PortData = Reg[ PortAddr ];

// Operation

always @ ( posedge CLK ) begin
   if ( PortWrite )
      Reg[ WritePort ] <= PortOut;
end

endmodule
