// Verilog model created from c:\xilinx\csse\alu\bitadder.sch - Fri Feb 20 20:31:28 2004

`timescale 1ns / 1ps

module bitadder2(a, b, ci, co, do, CLK);

    input a;
    input b;
    input ci;
    input CLK;
   output co;
   output do;
   
   wire ab;
   wire aci;
   wire bci;

always @ ( posedge CLK ) begin
   
   	AND2 XLXI_1 (.I0(b), .I1(a), .O(ab));
     AND2 XLXI_2 (.I0(ci), .I1(a), .O(aci));
     AND2 XLXI_3 (.I0(ci), .I1(b), .O(bci));
     XOR3 XLXI_4 (.I0(ci), .I1(b), .I2(a), .O(do));
     OR3 XLXI_5 (.I0(bci), .I1(aci), .I2(ab), .O(co));
end

endmodule