library verilog;
use verilog.vl_types.all;
entity portfile is
    generic(
        num_regs        : integer := 4
    );
    port(
        portaddr        : in     vl_logic_vector(1 downto 0);
        writeport       : in     vl_logic_vector(1 downto 0);
        portdata        : out    vl_logic_vector(15 downto 0);
        portwrite       : in     vl_logic;
        portout         : in     vl_logic_vector(15 downto 0);
        clk             : in     vl_logic
    );
end portfile;
