library verilog;
use verilog.vl_types.all;
entity onebitalu is
    port(
        a               : in     vl_logic;
        b               : in     vl_logic;
        binvert         : in     vl_logic;
        ci              : in     vl_logic;
        operation0      : in     vl_logic;
        operation1      : in     vl_logic;
        slt             : in     vl_logic;
        aaddb           : out    vl_logic;
        co              : out    vl_logic;
        result          : out    vl_logic
    );
end onebitalu;
