module Mux8(mux_out, data1,data2,data3,data4,data5,data6,data7,data0, controlin);

output [15:0] mux_out;
input [15:0] data0;
input [15:0] data1;
input [15:0] data2;
input [15:0] data3;
input [15:0] data4;
input [15:0] data5;
input [15:0] data6;
input [15:0] data7;
input [2:0] controlin;

reg [15:0] mux_out;

always @ (mux_out, data1,data2,data3,data4,data5,data6,data7,data0, controlin)

		case(controlin)
				
				0:	mux_out <= data0;
				1:	mux_out <= data1;
				2:	mux_out <= data2;
				3:	mux_out <= data3;
				4:	mux_out <= data4;
				5:	mux_out <= data5;
				6:	mux_out <= data6;
				7:	mux_out <= data7;
				default: mux_out <=16'bx;
		endcase
endmodule