library verilog;
use verilog.vl_types.all;
entity maindatapath is
    port(
        clock           : in     vl_logic;
        input           : in     vl_logic_vector(15 downto 0);
        irqin           : in     vl_logic_vector(1 downto 0);
        reset           : in     vl_logic;
        output          : out    vl_logic_vector(15 downto 0)
    );
end maindatapath;
