// Verilog model created from C:\Xilinx\spartan2\data\drawing\fd16ce.sch - Fri Feb 20 16:16:17 2004

`timescale 1ns / 1ps

module FD16CE_MXILINX_pc(C, CE, CLR, D, Q);

    input C;
    input CE;
    input CLR;
    input [15:0] D;
   output [15:0] Q;
   
   
   FDCE I_Q0 (.C(C), .CE(CE), .CLR(CLR), .D(D[0]), .Q(Q[0]));
   // synthesis attribute INIT of I_Q0 is "0"
   // synopsys translate_off
   defparam I_Q0.INIT = 1'b0;
   // synopsys translate_on
   FDCE I_Q1 (.C(C), .CE(CE), .CLR(CLR), .D(D[1]), .Q(Q[1]));
   // synthesis attribute INIT of I_Q1 is "0"
   // synopsys translate_off
   defparam I_Q1.INIT = 1'b0;
   // synopsys translate_on
   FDCE I_Q2 (.C(C), .CE(CE), .CLR(CLR), .D(D[2]), .Q(Q[2]));
   // synthesis attribute INIT of I_Q2 is "0"
   // synopsys translate_off
   defparam I_Q2.INIT = 1'b0;
   // synopsys translate_on
   FDCE I_Q3 (.C(C), .CE(CE), .CLR(CLR), .D(D[3]), .Q(Q[3]));
   // synthesis attribute INIT of I_Q3 is "0"
   // synopsys translate_off
   defparam I_Q3.INIT = 1'b0;
   // synopsys translate_on
   FDCE I_Q4 (.C(C), .CE(CE), .CLR(CLR), .D(D[4]), .Q(Q[4]));
   // synthesis attribute INIT of I_Q4 is "0"
   // synopsys translate_off
   defparam I_Q4.INIT = 1'b0;
   // synopsys translate_on
   FDCE I_Q5 (.C(C), .CE(CE), .CLR(CLR), .D(D[5]), .Q(Q[5]));
   // synthesis attribute INIT of I_Q5 is "0"
   // synopsys translate_off
   defparam I_Q5.INIT = 1'b0;
   // synopsys translate_on
   FDCE I_Q6 (.C(C), .CE(CE), .CLR(CLR), .D(D[6]), .Q(Q[6]));
   // synthesis attribute INIT of I_Q6 is "0"
   // synopsys translate_off
   defparam I_Q6.INIT = 1'b0;
   // synopsys translate_on
   FDCE I_Q7 (.C(C), .CE(CE), .CLR(CLR), .D(D[7]), .Q(Q[7]));
   // synthesis attribute INIT of I_Q7 is "0"
   // synopsys translate_off
   defparam I_Q7.INIT = 1'b0;
   // synopsys translate_on
   FDCE I_Q8 (.C(C), .CE(CE), .CLR(CLR), .D(D[8]), .Q(Q[8]));
   // synthesis attribute INIT of I_Q8 is "0"
   // synopsys translate_off
   defparam I_Q8.INIT = 1'b0;
   // synopsys translate_on
   FDCE I_Q9 (.C(C), .CE(CE), .CLR(CLR), .D(D[9]), .Q(Q[9]));
   // synthesis attribute INIT of I_Q9 is "0"
   // synopsys translate_off
   defparam I_Q9.INIT = 1'b0;
   // synopsys translate_on
   FDCE I_Q10 (.C(C), .CE(CE), .CLR(CLR), .D(D[10]), .Q(Q[10]));
   // synthesis attribute INIT of I_Q10 is "0"
   // synopsys translate_off
   defparam I_Q10.INIT = 1'b0;
   // synopsys translate_on
   FDCE I_Q11 (.C(C), .CE(CE), .CLR(CLR), .D(D[11]), .Q(Q[11]));
   // synthesis attribute INIT of I_Q11 is "0"
   // synopsys translate_off
   defparam I_Q11.INIT = 1'b0;
   // synopsys translate_on
   FDCE I_Q12 (.C(C), .CE(CE), .CLR(CLR), .D(D[12]), .Q(Q[12]));
   // synthesis attribute INIT of I_Q12 is "0"
   // synopsys translate_off
   defparam I_Q12.INIT = 1'b0;
   // synopsys translate_on
   FDCE I_Q13 (.C(C), .CE(CE), .CLR(CLR), .D(D[13]), .Q(Q[13]));
   // synthesis attribute INIT of I_Q13 is "0"
   // synopsys translate_off
   defparam I_Q13.INIT = 1'b0;
   // synopsys translate_on
   FDCE I_Q14 (.C(C), .CE(CE), .CLR(CLR), .D(D[14]), .Q(Q[14]));
   // synthesis attribute INIT of I_Q14 is "0"
   // synopsys translate_off
   defparam I_Q14.INIT = 1'b0;
   // synopsys translate_on
   FDCE I_Q15 (.C(C), .CE(CE), .CLR(CLR), .D(D[15]), .Q(Q[15]));
   // synthesis attribute INIT of I_Q15 is "0"
   // synopsys translate_off
   defparam I_Q15.INIT = 1'b0;
   // synopsys translate_on
endmodule
// Verilog model created from pc.sch - Fri Feb 20 16:16:17 2004

`timescale 1ns / 1ps

module pc(Clear, Clock, ClockEnable, Input, Output);

    input Clear;
    input Clock;
    input ClockEnable;
    input [15:0] Input;
   output [15:0] Output;
   
   
   FD16CE_MXILINX_pc XLXI_1 (.C(Clock), .CE(ClockEnable), .CLR(Clear),
         .D(Input[15:0]), .Q(Output[15:0]));
   // synthesis attribute HU_SET of XLXI_1 is "XLXI_1_0"
endmodule
