//  C:\XILINX\CSSE\MAINDATAPATH\CONTROL.v
//  Verilog created by Xilinx's StateCAD 6.1i
//  Sat Feb 21 11:23:46 2004

//  This Verilog code (for use with Xilinx XST) was generated using: 
//  one-hot state assignment with boolean code format.
//  Minimization is enabled,  implied else is enabled, 
//  and outputs are speed optimized.

`timescale 1s/1s

module shell_control(CLK,CtrlInterrupt,IR0,IR1,IR2,IR3,IR4,IR5,IR6,IR7,IR8,
	IR9,IR10,IR11,IR12,IR13,IR14,IR15,RESET,ALUOP0,ALUOP1,ALUSrcB0,ALUSrcB1,Check
	,EPCWrite,IEBClear,IEBControl,IorD,IRWrite,MemRead,MemtoReg0,MemtoReg1,
	MemtoReg2,MemWrite,PCSource0,PCSource1,PCSource2,PCWrite,PCWriteCond,
	PortWrite,RegBControl,RegDST0,RegDST1,RegWrite,SEControl);

	input CLK;
	input CtrlInterrupt,IR0,IR1,IR2,IR3,IR4,IR5,IR6,IR7,IR8,IR9,IR10,IR11,IR12,
		IR13,IR14,IR15,RESET;
	output ALUOP0,ALUOP1,ALUSrcB0,ALUSrcB1,Check,EPCWrite,IEBClear,IEBControl,
		IorD,IRWrite,MemRead,MemtoReg0,MemtoReg1,MemtoReg2,MemWrite,PCSource0,
		PCSource1,PCSource2,PCWrite,PCWriteCond,PortWrite,RegBControl,RegDST0,RegDST1
		,RegWrite,SEControl;

	reg [1:0] ALUOP;
	reg [1:0] ALUSrcB;
	reg [2:0] MemtoReg;
	reg [2:0] PCSource;
	reg [1:0] RegDST;
	reg ALUOP0,next_ALUOP0,ALUOP1,next_ALUOP1,ALUSrcB0,next_ALUSrcB0,ALUSrcB1,
		next_ALUSrcB1,Check,next_Check,EPCWrite,next_EPCWrite,IEBClear,next_IEBClear,
		IEBControl,next_IEBControl,IorD,next_IorD,IRWrite,next_IRWrite,MemRead,
		next_MemRead,MemtoReg0,next_MemtoReg0,MemtoReg1,next_MemtoReg1,MemtoReg2,
		next_MemtoReg2,MemWrite,next_MemWrite,PCSource0,next_PCSource0,PCSource1,
		next_PCSource1,PCSource2,next_PCSource2,PCWrite,next_PCWrite,PCWriteCond,
		next_PCWriteCond,PortWrite,next_PortWrite,RegBControl,next_RegBControl,
		RegDST0,next_RegDST0,RegDST1,next_RegDST1,RegWrite,next_RegWrite,SEControl,
		next_SEControl;
	reg ADD,next_ADD,BEQ,next_BEQ,CHECKINTERRUPT,next_CHECKINTERRUPT,DECODE,
		next_DECODE,FETCH,next_FETCH,INTERRUPT,next_INTERRUPT,ISRT,next_ISRT,JUMP,
		next_JUMP,JUMPANDLINK,next_JUMPANDLINK,JUMPREGISTER,next_JUMPREGISTER,LINPUT,
		next_LINPUT,LLI,next_LLI,LOADWORD,next_LOADWORD,LUI,next_LUI,RFI,next_RFI,
		SETLESSTHAN,next_SETLESSTHAN,SHIFTLEFTLOGICAL,next_SHIFTLEFTLOGICAL,SOUTPUT,
		next_SOUTPUT,SPECIALASSERT,next_SPECIALASSERT,Start,next_Start,STATE6,
		next_STATE6,STATE17,next_STATE17,STATE19,next_STATE19,STATE20,next_STATE20,
		STOREWORD,next_STOREWORD,SUB,next_SUB;

	always @(posedge CLK or posedge RESET)
	begin
		if ( RESET ) begin
			ADD = 0;
			BEQ = 0;
			CHECKINTERRUPT = 0;
			DECODE = 0;
			FETCH = 0;
			INTERRUPT = 0;
			ISRT = 0;
			JUMP = 0;
			JUMPANDLINK = 0;
			JUMPREGISTER = 0;
			LINPUT = 0;
			LLI = 0;
			LOADWORD = 0;
			LUI = 0;
			RFI = 0;
			SETLESSTHAN = 0;
			SHIFTLEFTLOGICAL = 0;
			SOUTPUT = 0;
			SPECIALASSERT = 0;
			Start = 1;
			STATE6 = 0;
			STATE17 = 0;
			STATE19 = 0;
			STATE20 = 0;
			STOREWORD = 0;
			SUB = 0;
			Check = 0;
			EPCWrite = 0;
			IEBControl = 0;
			IorD = 0;
			IRWrite = 0;
			MemRead = 0;
			MemWrite = 0;
			PCWrite = 0;
			PCWriteCond = 0;
			PortWrite = 0;
			RegBControl = 0;
			RegWrite = 0;
			SEControl = 0;
			ALUSrcB1 = 0;
			ALUSrcB0 = 0;
			MemtoReg2 = 0;
			MemtoReg1 = 0;
			MemtoReg0 = 0;
			PCSource2 = 0;
			PCSource1 = 0;
			PCSource0 = 0;
			RegDST1 = 0;
			RegDST0 = 0;
			IEBClear = 1;
			ALUOP1 = 0;
			ALUOP0 = 0;
		end else
		begin
			ADD = next_ADD;
			BEQ = next_BEQ;
			CHECKINTERRUPT = next_CHECKINTERRUPT;
			DECODE = next_DECODE;
			FETCH = next_FETCH;
			INTERRUPT = next_INTERRUPT;
			ISRT = next_ISRT;
			JUMP = next_JUMP;
			JUMPANDLINK = next_JUMPANDLINK;
			JUMPREGISTER = next_JUMPREGISTER;
			LINPUT = next_LINPUT;
			LLI = next_LLI;
			LOADWORD = next_LOADWORD;
			LUI = next_LUI;
			RFI = next_RFI;
			SETLESSTHAN = next_SETLESSTHAN;
			SHIFTLEFTLOGICAL = next_SHIFTLEFTLOGICAL;
			SOUTPUT = next_SOUTPUT;
			SPECIALASSERT = next_SPECIALASSERT;
			Start = next_Start;
			STATE6 = next_STATE6;
			STATE17 = next_STATE17;
			STATE19 = next_STATE19;
			STATE20 = next_STATE20;
			STOREWORD = next_STOREWORD;
			SUB = next_SUB;
			Check = next_Check;
			EPCWrite = next_EPCWrite;
			IEBClear = next_IEBClear;
			IEBControl = next_IEBControl;
			IorD = next_IorD;
			IRWrite = next_IRWrite;
			MemRead = next_MemRead;
			MemWrite = next_MemWrite;
			PCWrite = next_PCWrite;
			PCWriteCond = next_PCWriteCond;
			PortWrite = next_PortWrite;
			RegBControl = next_RegBControl;
			RegWrite = next_RegWrite;
			SEControl = next_SEControl;
			ALUOP1 = next_ALUOP1;
			ALUOP0 = next_ALUOP0;
			ALUSrcB1 = next_ALUSrcB1;
			ALUSrcB0 = next_ALUSrcB0;
			MemtoReg2 = next_MemtoReg2;
			MemtoReg1 = next_MemtoReg1;
			MemtoReg0 = next_MemtoReg0;
			PCSource2 = next_PCSource2;
			PCSource1 = next_PCSource1;
			PCSource0 = next_PCSource0;
			RegDST1 = next_RegDST1;
			RegDST0 = next_RegDST0;
		end
	end

	always @ (ADD or BEQ or CHECKINTERRUPT or CtrlInterrupt or DECODE or FETCH 
		or INTERRUPT or IR10 or IR11 or IR12 or IR13 or IR14 or IR15 or ISRT or JUMP 
		or JUMPANDLINK or JUMPREGISTER or LINPUT or LLI or LOADWORD or LUI or RFI or 
		SETLESSTHAN or SHIFTLEFTLOGICAL or SOUTPUT or SPECIALASSERT or Start or 
		STATE6 or STATE17 or STATE19 or STATE20 or STOREWORD or SUB or ALUOP or 
		ALUSrcB or MemtoReg or PCSource or RegDST)
	begin

		if ( ~IR15 & ~IR14 & ~IR13 & ~IR12 & DECODE ) next_ADD=1;
		else next_ADD=0;

		if ( ~IR15 & IR14 & ~IR13 & IR12 & DECODE ) next_BEQ=1;
		else next_BEQ=0;

		if ( BEQ | INTERRUPT | ISRT | JUMP | JUMPREGISTER | LINPUT | LLI | LUI | 
			RFI | SETLESSTHAN | SHIFTLEFTLOGICAL | SOUTPUT | SPECIALASSERT | Start | 
			STATE6 | STATE17 | STATE20 ) next_CHECKINTERRUPT=1;
		else next_CHECKINTERRUPT=0;

		if ( IR15 & IR12 & IR13 & ~IR14 & DECODE | FETCH ) next_DECODE=1;
		else next_DECODE=0;

		if ( ~CtrlInterrupt & CHECKINTERRUPT ) next_FETCH=1;
		else next_FETCH=0;

		if ( CtrlInterrupt & CHECKINTERRUPT ) next_INTERRUPT=1;
		else next_INTERRUPT=0;

		if ( IR15 & IR14 & IR13 & IR12 & ~IR11 & ~IR10 & DECODE ) next_ISRT=1;
		else next_ISRT=0;

		if ( ~IR15 & ~IR14 & IR13 & IR12 & DECODE | JUMPANDLINK ) next_JUMP=1;
		else next_JUMP=0;

		if ( ~IR15 & IR14 & ~IR13 & ~IR12 & DECODE ) next_JUMPANDLINK=1;
		else next_JUMPANDLINK=0;

		if ( IR15 & IR14 & ~IR13 & ~IR12 & DECODE ) next_JUMPREGISTER=1;
		else next_JUMPREGISTER=0;

		if ( IR15 & IR14 & IR13 & ~IR12 & DECODE ) next_LINPUT=1;
		else next_LINPUT=0;

		if ( ~IR15 & IR14 & IR13 & IR12 & DECODE ) next_LLI=1;
		else next_LLI=0;

		if ( IR15 & ~IR14 & ~IR13 & IR12 & DECODE ) next_LOADWORD=1;
		else next_LOADWORD=0;

		if ( ~IR15 & IR14 & IR13 & ~IR12 & DECODE ) next_LUI=1;
		else next_LUI=0;

		if ( IR15 & IR14 & IR13 & IR12 & ~IR11 & IR10 & DECODE ) next_RFI=1;
		else next_RFI=0;

		if ( IR15 & ~IR14 & ~IR13 & ~IR12 & DECODE ) next_SETLESSTHAN=1;
		else next_SETLESSTHAN=0;

		if ( ~IR15 & ~IR14 & IR13 & ~IR12 & DECODE ) next_SHIFTLEFTLOGICAL=1;
		else next_SHIFTLEFTLOGICAL=0;

		if ( IR15 & IR14 & ~IR13 & IR12 & DECODE ) next_SOUTPUT=1;
		else next_SOUTPUT=0;

		if ( IR15 & IR14 & IR13 & IR12 & IR11 & DECODE ) next_SPECIALASSERT=1;
		else next_SPECIALASSERT=0;

		next_Start=0;

		if ( ADD | SUB ) next_STATE6=1;
		else next_STATE6=0;

		if ( STOREWORD ) next_STATE17=1;
		else next_STATE17=0;

		if ( LOADWORD ) next_STATE19=1;
		else next_STATE19=0;

		if ( STATE19 ) next_STATE20=1;
		else next_STATE20=0;

		if ( IR15 & ~IR14 & IR13 & ~IR12 & DECODE ) next_STOREWORD=1;
		else next_STOREWORD=0;

		if ( ~IR15 & ~IR14 & ~IR13 & IR12 & DECODE ) next_SUB=1;
		else next_SUB=0;


		ALUOP= ( {2{DECODE}}  & ( {2{~IR15}} & {2{~IR14}} & {2{~IR13}} & {2{~IR12}}
			  ) & ( 'h0 ) ) | ( {2{ADD}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{
			~IR15}} & {2{IR14}} & {2{~IR13}} & {2{IR12}}  ) & ( 'h1 ) ) | ( {2{BEQ}}  & (
			 2'h3 ) & ( 'h0 ) ) | ( {2{CHECKINTERRUPT}}  & ( {2{CtrlInterrupt}}  ) & ( 
			'h0 ) ) | ( {2{DECODE}}  & ( {2{IR15}} & {2{IR12}} & {2{IR13}} & {2{~IR14}}  
			) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{~IR15}} & {2{~IR14}} & {2{IR13}} & {2{~
			IR12}}  ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{~IR15}} & {2{~IR14}} & {2{IR13
			}} & {2{IR12}}  ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{~IR15}} & {2{IR14}} & 
			{2{~IR13}} & {2{~IR12}}  ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{IR15}} & {2{
			IR14}} & {2{~IR13}} & {2{~IR12}}  ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{~IR15
			}} & {2{IR14}} & {2{IR13}} & {2{~IR12}}  ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( 
			{2{~IR15}} & {2{IR14}} & {2{IR13}} & {2{IR12}}  ) & ( 'h0 ) ) | ( {2{DECODE}}
			  & ( {2{IR15}} & {2{IR14}} & {2{IR13}} & {2{IR12}} & {2{IR11}} & {2{~IR10}} 
			 ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{IR15}} & {2{IR14}} & {2{IR13}} & {2{
			IR12}} & {2{~IR11}} & {2{~IR10}}  ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{IR15
			}} & {2{IR14}} & {2{IR13}} & {2{~IR12}}  ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( 
			{2{IR15}} & {2{IR14}} & {2{~IR13}} & {2{IR12}}  ) & ( 'h0 ) ) | ( {2{DECODE}}
			  & ( {2{IR15}} & {2{IR14}} & {2{IR13}} & {2{IR12}} & {2{~IR11}} & {2{IR10}} 
			 ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{IR15}} & {2{IR14}} & {2{IR13}} & {2{
			IR12}} & {2{IR11}} & {2{IR10}}  ) & ( 'h0 ) ) | ( {2{CHECKINTERRUPT}}  & ( 
			{2{~CtrlInterrupt}}  ) & ( 'h0 ) ) | ( {2{FETCH}}  & ( 2'h3 ) & ( 'h0 ) ) | (
			 {2{INTERRUPT}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{ISRT}}  & ( 2'h3 ) & ( 'h0 ) )
			 | ( {2{JUMP}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{JUMPANDLINK}}  & ( 2'h3 ) & ( 
			'h0 ) ) | ( {2{JUMPREGISTER}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{LINPUT}}  & ( 
			2'h3 ) & ( 'h0 ) ) | ( {2{LLI}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( 
			{2{IR15}} & {2{~IR14}} & {2{~IR13}} & {2{IR12}}  ) & ( 'h0 ) ) | ( {2{
			LOADWORD}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{LUI}}  & ( 2'h3 ) & ( 'h0 ) ) | ( 
			{2{RFI}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{IR15}} & {2{~IR14}} 
			& {2{~IR13}} & {2{~IR12}}  ) & ( 'h2 ) ) | ( {2{SETLESSTHAN}}  & ( 2'h3 ) & (
			 'h0 ) ) | ( {2{SHIFTLEFTLOGICAL}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{SOUTPUT}}  
			& ( 2'h3 ) & ( 'h0 ) ) | ( {2{SPECIALASSERT}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{
			Start}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{STATE6}}  & ( 2'h3 ) & ( 'h0 ) ) | ( 
			{2{STATE17}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{STATE19}}  & ( 2'h3 ) & ( 'h0 ) )
			 | ( {2{STATE20}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{IR15}} & 
			{2{~IR14}} & {2{IR13}} & {2{~IR12}}  ) & ( 'h0 ) ) | ( {2{STOREWORD}}  & ( 
			2'h3 ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{~IR15}} & {2{~IR14}} & {2{~IR13}} 
			& {2{IR12}}  ) & ( 'h1 ) ) | ( {2{SUB}}  & ( 2'h3 ) & ( 'h0 ) );

		ALUSrcB= ( {2{DECODE}}  & ( {2{~IR15}} & {2{~IR14}} & {2{~IR13}} & {2{~IR12
			}}  ) & ( 'h0 ) ) | ( {2{ADD}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( 
			{2{~IR15}} & {2{IR14}} & {2{~IR13}} & {2{IR12}}  ) & ( 'h0 ) ) | ( {2{BEQ}}  
			& ( 2'h3 ) & ( 'h0 ) ) | ( {2{CHECKINTERRUPT}}  & ( {2{CtrlInterrupt}}  ) & (
			 'h0 ) ) | ( {2{DECODE}}  & ( {2{IR15}} & {2{IR12}} & {2{IR13}} & {2{~IR14}} 
			 ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{~IR15}} & {2{~IR14}} & {2{IR13}} & {2{
			~IR12}}  ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{~IR15}} & {2{~IR14}} & {2{IR13
			}} & {2{IR12}}  ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{~IR15}} & {2{IR14}} & 
			{2{~IR13}} & {2{~IR12}}  ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{IR15}} & {2{
			IR14}} & {2{~IR13}} & {2{~IR12}}  ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{~IR15
			}} & {2{IR14}} & {2{IR13}} & {2{~IR12}}  ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( 
			{2{~IR15}} & {2{IR14}} & {2{IR13}} & {2{IR12}}  ) & ( 'h0 ) ) | ( {2{DECODE}}
			  & ( {2{IR15}} & {2{IR14}} & {2{IR13}} & {2{IR12}} & {2{IR11}} & {2{~IR10}} 
			 ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{IR15}} & {2{IR14}} & {2{IR13}} & {2{
			IR12}} & {2{~IR11}} & {2{~IR10}}  ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{IR15
			}} & {2{IR14}} & {2{IR13}} & {2{~IR12}}  ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( 
			{2{IR15}} & {2{IR14}} & {2{~IR13}} & {2{IR12}}  ) & ( 'h0 ) ) | ( {2{DECODE}}
			  & ( {2{IR15}} & {2{IR14}} & {2{IR13}} & {2{IR12}} & {2{~IR11}} & {2{IR10}} 
			 ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{IR15}} & {2{IR14}} & {2{IR13}} & {2{
			IR12}} & {2{IR11}} & {2{IR10}}  ) & ( 'h0 ) ) | ( {2{CHECKINTERRUPT}}  & ( 
			{2{~CtrlInterrupt}}  ) & ( 'h2 ) ) | ( {2{FETCH}}  & ( 2'h3 ) & ( 'h0 ) ) | (
			 {2{INTERRUPT}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{ISRT}}  & ( 2'h3 ) & ( 'h0 ) )
			 | ( {2{JUMP}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{JUMPANDLINK}}  & ( 2'h3 ) & ( 
			'h0 ) ) | ( {2{JUMPREGISTER}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{LINPUT}}  & ( 
			2'h3 ) & ( 'h0 ) ) | ( {2{LLI}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( 
			{2{IR15}} & {2{~IR14}} & {2{~IR13}} & {2{IR12}}  ) & ( 'h1 ) ) | ( {2{
			LOADWORD}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{LUI}}  & ( 2'h3 ) & ( 'h0 ) ) | ( 
			{2{RFI}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{IR15}} & {2{~IR14}} 
			& {2{~IR13}} & {2{~IR12}}  ) & ( 'h0 ) ) | ( {2{SETLESSTHAN}}  & ( 2'h3 ) & (
			 'h0 ) ) | ( {2{SHIFTLEFTLOGICAL}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{SOUTPUT}}  
			& ( 2'h3 ) & ( 'h0 ) ) | ( {2{SPECIALASSERT}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{
			Start}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{STATE6}}  & ( 2'h3 ) & ( 'h0 ) ) | ( 
			{2{STATE17}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{STATE19}}  & ( 2'h3 ) & ( 'h0 ) )
			 | ( {2{STATE20}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{IR15}} & 
			{2{~IR14}} & {2{IR13}} & {2{~IR12}}  ) & ( 'h1 ) ) | ( {2{STOREWORD}}  & ( 
			2'h3 ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{~IR15}} & {2{~IR14}} & {2{~IR13}} 
			& {2{IR12}}  ) & ( 'h0 ) ) | ( {2{SUB}}  & ( 2'h3 ) & ( 'h0 ) );

		if ( BEQ | INTERRUPT | ISRT | JUMP | JUMPREGISTER | LINPUT | LLI | LUI | 
			RFI | SETLESSTHAN | SHIFTLEFTLOGICAL | SOUTPUT | SPECIALASSERT | Start | 
			STATE6 | STATE17 | STATE20 ) next_Check=1;
		else next_Check=0;

		if ( CtrlInterrupt & CHECKINTERRUPT ) next_EPCWrite=1;
		else next_EPCWrite=0;

		if ( CtrlInterrupt & CHECKINTERRUPT ) next_IEBClear=1;
		else next_IEBClear=0;

		if ( IR15 & IR14 & IR13 & IR12 & ~IR11 & DECODE ) next_IEBControl=1;
		else next_IEBControl=0;

		if ( STOREWORD | LOADWORD ) next_IorD=1;
		else next_IorD=0;

		if ( ~CtrlInterrupt & CHECKINTERRUPT ) next_IRWrite=1;
		else next_IRWrite=0;

		if ( ~CtrlInterrupt & CHECKINTERRUPT | LOADWORD ) next_MemRead=1;
		else next_MemRead=0;

		MemtoReg= ( {3{BEQ}}  & ( 3'h7 ) & ( 'h0 ) ) | ( {3{CHECKINTERRUPT}}  & ( 
			{3{CtrlInterrupt}}  ) & ( 'h0 ) ) | ( {3{CHECKINTERRUPT}}  & ( {3{~
			CtrlInterrupt}}  ) & ( 'h0 ) ) | ( {3{DECODE}}  & ( {3{IR15}} & {3{IR12}} & 
			{3{IR13}} & {3{~IR14}}  ) & ( 'h0 ) ) | ( {3{DECODE}}  & ( {3{~IR15}} & {3{~
			IR14}} & {3{~IR13}} & {3{~IR12}}  ) & ( 'h0 ) ) | ( {3{DECODE}}  & ( {3{~IR15
			}} & {3{~IR14}} & {3{~IR13}} & {3{IR12}}  ) & ( 'h0 ) ) | ( {3{DECODE}}  & ( 
			{3{~IR15}} & {3{~IR14}} & {3{IR13}} & {3{IR12}}  ) & ( 'h0 ) ) | ( {3{DECODE
			}}  & ( {3{IR15}} & {3{IR14}} & {3{~IR13}} & {3{~IR12}}  ) & ( 'h0 ) ) | ( 
			{3{DECODE}}  & ( {3{~IR15}} & {3{IR14}} & {3{~IR13}} & {3{IR12}}  ) & ( 'h0 )
			 ) | ( {3{DECODE}}  & ( {3{IR15}} & {3{~IR14}} & {3{IR13}} & {3{~IR12}}  ) & 
			( 'h0 ) ) | ( {3{DECODE}}  & ( {3{IR15}} & {3{~IR14}} & {3{~IR13}} & {3{IR12
			}}  ) & ( 'h0 ) ) | ( {3{DECODE}}  & ( {3{IR15}} & {3{IR14}} & {3{IR13}} & 
			{3{IR12}} & {3{IR11}} & {3{~IR10}}  ) & ( 'h0 ) ) | ( {3{DECODE}}  & ( {3{
			IR15}} & {3{IR14}} & {3{IR13}} & {3{IR12}} & {3{~IR11}} & {3{~IR10}}  ) & ( 
			'h0 ) ) | ( {3{DECODE}}  & ( {3{IR15}} & {3{IR14}} & {3{~IR13}} & {3{IR12}}  
			) & ( 'h0 ) ) | ( {3{DECODE}}  & ( {3{IR15}} & {3{IR14}} & {3{IR13}} & {3{
			IR12}} & {3{~IR11}} & {3{IR10}}  ) & ( 'h0 ) ) | ( {3{DECODE}}  & ( {3{IR15}}
			 & {3{IR14}} & {3{IR13}} & {3{IR12}} & {3{IR11}} & {3{IR10}}  ) & ( 'h0 ) ) |
			 ( {3{FETCH}}  & ( 3'h7 ) & ( 'h0 ) ) | ( {3{INTERRUPT}}  & ( 3'h7 ) & ( 'h0 
			) ) | ( {3{ISRT}}  & ( 3'h7 ) & ( 'h0 ) ) | ( {3{JUMP}}  & ( 3'h7 ) & ( 'h0 )
			 ) | ( {3{DECODE}}  & ( {3{~IR15}} & {3{IR14}} & {3{~IR13}} & {3{~IR12}}  ) &
			 ( 'h1 ) ) | ( {3{JUMPANDLINK}}  & ( 3'h7 ) & ( 'h0 ) ) | ( {3{JUMPREGISTER}}
			  & ( 3'h7 ) & ( 'h0 ) ) | ( {3{DECODE}}  & ( {3{IR15}} & {3{IR14}} & {3{IR13
			}} & {3{~IR12}}  ) & ( 'h7 ) ) | ( {3{LINPUT}}  & ( 3'h7 ) & ( 'h0 ) ) | ( 
			{3{DECODE}}  & ( {3{~IR15}} & {3{IR14}} & {3{IR13}} & {3{IR12}}  ) & ( 'h5 ) 
			) | ( {3{LLI}}  & ( 3'h7 ) & ( 'h0 ) ) | ( {3{LOADWORD}}  & ( 3'h7 ) & ( 'h0 
			) ) | ( {3{DECODE}}  & ( {3{~IR15}} & {3{IR14}} & {3{IR13}} & {3{~IR12}}  ) &
			 ( 'h0 ) ) | ( {3{LUI}}  & ( 3'h7 ) & ( 'h0 ) ) | ( {3{RFI}}  & ( 3'h7 ) & ( 
			'h0 ) ) | ( {3{DECODE}}  & ( {3{IR15}} & {3{~IR14}} & {3{~IR13}} & {3{~IR12}}
			  ) & ( 'h6 ) ) | ( {3{SETLESSTHAN}}  & ( 3'h7 ) & ( 'h0 ) ) | ( {3{DECODE}} 
			 & ( {3{~IR15}} & {3{~IR14}} & {3{IR13}} & {3{~IR12}}  ) & ( 'h2 ) ) | ( {3{
			SHIFTLEFTLOGICAL}}  & ( 3'h7 ) & ( 'h0 ) ) | ( {3{SOUTPUT}}  & ( 3'h7 ) & ( 
			'h0 ) ) | ( {3{SPECIALASSERT}}  & ( 3'h7 ) & ( 'h0 ) ) | ( {3{Start}}  & ( 
			3'h7 ) & ( 'h0 ) ) | ( {3{ADD}}  & ( 3'h7 ) & ( 'h4 ) ) | ( {3{SUB}}  & ( 
			3'h7 ) & ( 'h4 ) ) | ( {3{STATE6}}  & ( 3'h7 ) & ( 'h0 ) ) | ( {3{STATE17}}  
			& ( 3'h7 ) & ( 'h0 ) ) | ( {3{STATE19}}  & ( 3'h7 ) & ( 'h3 ) ) | ( {3{
			STATE20}}  & ( 3'h7 ) & ( 'h0 ) ) | ( {3{STOREWORD}}  & ( 3'h7 ) & ( 'h0 ) );

		if ( STOREWORD ) next_MemWrite=1;
		else next_MemWrite=0;

		PCSource= ( {3{ADD}}  & ( 3'h7 ) & ( 'h0 ) ) | ( {3{DECODE}}  & ( {3{~IR15
			}} & {3{IR14}} & {3{~IR13}} & {3{IR12}}  ) & ( 'h5 ) ) | ( {3{BEQ}}  & ( 3'h7
			 ) & ( 'h0 ) ) | ( {3{DECODE}}  & ( {3{IR15}} & {3{IR12}} & {3{IR13}} & {3{~
			IR14}}  ) & ( 'h0 ) ) | ( {3{DECODE}}  & ( {3{~IR15}} & {3{~IR14}} & {3{~IR13
			}} & {3{~IR12}}  ) & ( 'h0 ) ) | ( {3{DECODE}}  & ( {3{~IR15}} & {3{~IR14}} &
			 {3{~IR13}} & {3{IR12}}  ) & ( 'h0 ) ) | ( {3{DECODE}}  & ( {3{~IR15}} & {3{~
			IR14}} & {3{IR13}} & {3{~IR12}}  ) & ( 'h0 ) ) | ( {3{DECODE}}  & ( {3{~IR15
			}} & {3{IR14}} & {3{~IR13}} & {3{~IR12}}  ) & ( 'h0 ) ) | ( {3{DECODE}}  & ( 
			{3{~IR15}} & {3{IR14}} & {3{IR13}} & {3{~IR12}}  ) & ( 'h0 ) ) | ( {3{DECODE
			}}  & ( {3{~IR15}} & {3{IR14}} & {3{IR13}} & {3{IR12}}  ) & ( 'h0 ) ) | ( {3{
			DECODE}}  & ( {3{IR15}} & {3{~IR14}} & {3{~IR13}} & {3{~IR12}}  ) & ( 'h0 ) )
			 | ( {3{DECODE}}  & ( {3{IR15}} & {3{~IR14}} & {3{IR13}} & {3{~IR12}}  ) & ( 
			'h0 ) ) | ( {3{DECODE}}  & ( {3{IR15}} & {3{~IR14}} & {3{~IR13}} & {3{IR12}} 
			 ) & ( 'h0 ) ) | ( {3{DECODE}}  & ( {3{IR15}} & {3{IR14}} & {3{IR13}} & {3{
			IR12}} & {3{IR11}} & {3{~IR10}}  ) & ( 'h0 ) ) | ( {3{DECODE}}  & ( {3{IR15}}
			 & {3{IR14}} & {3{IR13}} & {3{IR12}} & {3{~IR11}} & {3{~IR10}}  ) & ( 'h0 ) )
			 | ( {3{DECODE}}  & ( {3{IR15}} & {3{IR14}} & {3{IR13}} & {3{~IR12}}  ) & ( 
			'h0 ) ) | ( {3{DECODE}}  & ( {3{IR15}} & {3{IR14}} & {3{~IR13}} & {3{IR12}}  
			) & ( 'h0 ) ) | ( {3{DECODE}}  & ( {3{IR15}} & {3{IR14}} & {3{IR13}} & {3{
			IR12}} & {3{IR11}} & {3{IR10}}  ) & ( 'h0 ) ) | ( {3{CHECKINTERRUPT}}  & ( 
			{3{~CtrlInterrupt}}  ) & ( 'h4 ) ) | ( {3{FETCH}}  & ( 3'h7 ) & ( 'h0 ) ) | (
			 {3{CHECKINTERRUPT}}  & ( {3{CtrlInterrupt}}  ) & ( 'h3 ) ) | ( {3{INTERRUPT
			}}  & ( 3'h7 ) & ( 'h0 ) ) | ( {3{ISRT}}  & ( 3'h7 ) & ( 'h0 ) ) | ( {3{
			DECODE}}  & ( {3{~IR15}} & {3{~IR14}} & {3{IR13}} & {3{IR12}}  ) & ( 'h0 ) ) 
			| ( {3{JUMPANDLINK}}  & ( 3'h7 ) & ( 'h0 ) ) | ( {3{JUMP}}  & ( 3'h7 ) & ( 
			'h0 ) ) | ( {3{DECODE}}  & ( {3{IR15}} & {3{IR14}} & {3{~IR13}} & {3{~IR12}} 
			 ) & ( 'h1 ) ) | ( {3{JUMPREGISTER}}  & ( 3'h7 ) & ( 'h0 ) ) | ( {3{LINPUT}} 
			 & ( 3'h7 ) & ( 'h0 ) ) | ( {3{LLI}}  & ( 3'h7 ) & ( 'h0 ) ) | ( {3{LOADWORD
			}}  & ( 3'h7 ) & ( 'h0 ) ) | ( {3{LUI}}  & ( 3'h7 ) & ( 'h0 ) ) | ( {3{DECODE
			}}  & ( {3{IR15}} & {3{IR14}} & {3{IR13}} & {3{IR12}} & {3{~IR11}} & {3{IR10
			}}  ) & ( 'h2 ) ) | ( {3{RFI}}  & ( 3'h7 ) & ( 'h0 ) ) | ( {3{SETLESSTHAN}}  
			& ( 3'h7 ) & ( 'h0 ) ) | ( {3{SHIFTLEFTLOGICAL}}  & ( 3'h7 ) & ( 'h0 ) ) | ( 
			{3{SOUTPUT}}  & ( 3'h7 ) & ( 'h0 ) ) | ( {3{SPECIALASSERT}}  & ( 3'h7 ) & ( 
			'h0 ) ) | ( {3{Start}}  & ( 3'h7 ) & ( 'h0 ) ) | ( {3{STATE6}}  & ( 3'h7 ) & 
			( 'h0 ) ) | ( {3{STATE17}}  & ( 3'h7 ) & ( 'h0 ) ) | ( {3{STATE19}}  & ( 3'h7
			 ) & ( 'h0 ) ) | ( {3{STATE20}}  & ( 3'h7 ) & ( 'h0 ) ) | ( {3{STOREWORD}}  &
			 ( 3'h7 ) & ( 'h0 ) ) | ( {3{SUB}}  & ( 3'h7 ) & ( 'h0 ) );

		if ( CHECKINTERRUPT | ~IR15 & ~IR14 & IR13 & IR12 & DECODE | JUMPANDLINK | 
			IR15 & IR14 & ~IR13 & ~IR12 & DECODE | IR15 & IR14 & IR13 & IR12 & ~IR11 & 
			IR10 & DECODE ) next_PCWrite=1;
		else next_PCWrite=0;

		if ( ~IR15 & IR14 & ~IR13 & IR12 & DECODE ) next_PCWriteCond=1;
		else next_PCWriteCond=0;

		if ( IR15 & IR14 & IR13 & IR12 & IR11 & DECODE ) next_PortWrite=1;
		else next_PortWrite=0;

		if ( IR15 & IR12 & IR13 & ~IR14 & DECODE | FETCH ) next_RegBControl=1;
		else next_RegBControl=0;

		RegDST= ( {2{BEQ}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{CHECKINTERRUPT}}  & ( {2{
			CtrlInterrupt}}  ) & ( 'h0 ) ) | ( {2{CHECKINTERRUPT}}  & ( {2{~CtrlInterrupt
			}}  ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{IR15}} & {2{IR12}} & {2{IR13}} & 
			{2{~IR14}}  ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{~IR15}} & {2{~IR14}} & {2{~
			IR13}} & {2{~IR12}}  ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{~IR15}} & {2{~IR14
			}} & {2{~IR13}} & {2{IR12}}  ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{~IR15}} & 
			{2{~IR14}} & {2{IR13}} & {2{IR12}}  ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{
			IR15}} & {2{IR14}} & {2{~IR13}} & {2{~IR12}}  ) & ( 'h0 ) ) | ( {2{DECODE}}  
			& ( {2{~IR15}} & {2{IR14}} & {2{~IR13}} & {2{IR12}}  ) & ( 'h0 ) ) | ( {2{
			DECODE}}  & ( {2{IR15}} & {2{~IR14}} & {2{IR13}} & {2{~IR12}}  ) & ( 'h0 ) ) 
			| ( {2{DECODE}}  & ( {2{IR15}} & {2{~IR14}} & {2{~IR13}} & {2{IR12}}  ) & ( 
			'h0 ) ) | ( {2{DECODE}}  & ( {2{IR15}} & {2{IR14}} & {2{IR13}} & {2{IR12}} & 
			{2{IR11}} & {2{~IR10}}  ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{IR15}} & {2{
			IR14}} & {2{IR13}} & {2{IR12}} & {2{~IR11}} & {2{~IR10}}  ) & ( 'h0 ) ) | ( 
			{2{DECODE}}  & ( {2{IR15}} & {2{IR14}} & {2{~IR13}} & {2{IR12}}  ) & ( 'h0 ) 
			) | ( {2{DECODE}}  & ( {2{IR15}} & {2{IR14}} & {2{IR13}} & {2{IR12}} & {2{~
			IR11}} & {2{IR10}}  ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{IR15}} & {2{IR14}} 
			& {2{IR13}} & {2{IR12}} & {2{IR11}} & {2{IR10}}  ) & ( 'h0 ) ) | ( {2{FETCH}}
			  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{INTERRUPT}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{
			ISRT}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{JUMP}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{
			DECODE}}  & ( {2{~IR15}} & {2{IR14}} & {2{~IR13}} & {2{~IR12}}  ) & ( 'h1 ) )
			 | ( {2{JUMPANDLINK}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{JUMPREGISTER}}  & ( 2'h3
			 ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{IR15}} & {2{IR14}} & {2{IR13}} & {2{~
			IR12}}  ) & ( 'h0 ) ) | ( {2{LINPUT}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{DECODE}}
			  & ( {2{~IR15}} & {2{IR14}} & {2{IR13}} & {2{IR12}}  ) & ( 'h2 ) ) | ( {2{
			LLI}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{LOADWORD}}  & ( 2'h3 ) & ( 'h0 ) ) | ( 
			{2{DECODE}}  & ( {2{~IR15}} & {2{IR14}} & {2{IR13}} & {2{~IR12}}  ) & ( 'h2 )
			 ) | ( {2{LUI}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{RFI}}  & ( 2'h3 ) & ( 'h0 ) ) 
			| ( {2{DECODE}}  & ( {2{IR15}} & {2{~IR14}} & {2{~IR13}} & {2{~IR12}}  ) & ( 
			'h0 ) ) | ( {2{SETLESSTHAN}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{DECODE}}  & ( {2{
			~IR15}} & {2{~IR14}} & {2{IR13}} & {2{~IR12}}  ) & ( 'h0 ) ) | ( {2{
			SHIFTLEFTLOGICAL}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{SOUTPUT}}  & ( 2'h3 ) & ( 
			'h0 ) ) | ( {2{SPECIALASSERT}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{Start}}  & ( 
			2'h3 ) & ( 'h0 ) ) | ( {2{ADD}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{SUB}}  & ( 
			2'h3 ) & ( 'h0 ) ) | ( {2{STATE6}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{STATE17}}  
			& ( 2'h3 ) & ( 'h0 ) ) | ( {2{STATE19}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{
			STATE20}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{STOREWORD}}  & ( 2'h3 ) & ( 'h0 ) );

		if ( IR14 & IR13 & ~IR12 & DECODE | ~IR15 & IR14 & IR13 & DECODE | ~IR15 & 
			IR14 & ~IR12 & DECODE | IR15 & ~IR14 & ~IR13 & ~IR12 & DECODE | ~IR15 & IR13 
			& ~IR12 & DECODE | ADD | SUB | STATE19 ) next_RegWrite=1;
		else next_RegWrite=0;

		if ( ~IR15 & IR14 & IR13 & IR12 & DECODE | IR15 & ~IR14 & IR13 & ~IR12 & 
			DECODE ) next_SEControl=1;
		else next_SEControl=0;

		next_ALUOP1 = ALUOP[1];
		next_ALUOP0 = ALUOP[0];
		next_ALUSrcB1 = ALUSrcB[1];
		next_ALUSrcB0 = ALUSrcB[0];
		next_MemtoReg2 = MemtoReg[2];
		next_MemtoReg1 = MemtoReg[1];
		next_MemtoReg0 = MemtoReg[0];
		next_PCSource2 = PCSource[2];
		next_PCSource1 = PCSource[1];
		next_PCSource0 = PCSource[0];
		next_RegDST1 = RegDST[1];
		next_RegDST0 = RegDST[0];
	end
endmodule

module control(ALUOP,ALUSrcB,IR,MemtoReg,PCSource,RegDST,CLK,CtrlInterrupt,
	RESET,Check,EPCWrite,IEBClear,IEBControl,IorD,IRWrite,MemRead,MemWrite,
	PCWrite,PCWriteCond,PortWrite,RegBControl,RegWrite,SEControl);

	output [1:0] ALUOP;
	output [1:0] ALUSrcB;
	input [15:0] IR;
	output [2:0] MemtoReg;
	output [2:0] PCSource;
	output [1:0] RegDST;
	input CLK;
	input CtrlInterrupt,RESET;
	output Check,EPCWrite,IEBClear,IEBControl,IorD,IRWrite,MemRead,MemWrite,
		PCWrite,PCWriteCond,PortWrite,RegBControl,RegWrite,SEControl;

	wire [1:0] ALUOP;
	wire [1:0] ALUSrcB;
	wire [15:0] IR;
	wire [2:0] MemtoReg;
	wire [2:0] PCSource;
	wire [1:0] RegDST;
	wire CLK;
	wire CtrlInterrupt,RESET;
	wire Check,EPCWrite,IEBClear,IEBControl,IorD,IRWrite,MemRead,MemWrite,
		PCWrite,PCWriteCond,PortWrite,RegBControl,RegWrite,SEControl;

	shell_control part1(.CLK(CLK),.CtrlInterrupt(CtrlInterrupt),.IR0(IR[0]),.IR1
		(IR[1]),.IR2(IR[2]),.IR3(IR[3]),.IR4(IR[4]),.IR5(IR[5]),.IR6(IR[6]),.IR7(
		IR[7]),.IR8(IR[8]),.IR9(IR[9]),.IR10(IR[10]),.IR11(IR[11]),.IR12(IR[12]),
		.IR13(IR[13]),.IR14(IR[14]),.IR15(IR[15]),.RESET(RESET),.ALUOP0(ALUOP[0]),
		.ALUOP1(ALUOP[1]),.ALUSrcB0(ALUSrcB[0]),.ALUSrcB1(ALUSrcB[1]),.Check(Check),
		.EPCWrite(EPCWrite),.IEBClear(IEBClear),.IEBControl(IEBControl),.IorD(IorD),
		.IRWrite(IRWrite),.MemRead(MemRead),.MemtoReg0(MemtoReg[0]),.MemtoReg1(
		MemtoReg[1]),.MemtoReg2(MemtoReg[2]),.MemWrite(MemWrite),.PCSource0(
		PCSource[0]),.PCSource1(PCSource[1]),.PCSource2(PCSource[2]),.PCWrite(PCWrite
		),.PCWriteCond(PCWriteCond),.PortWrite(PortWrite),.RegBControl(RegBControl),
		.RegDST0(RegDST[0]),.RegDST1(RegDST[1]),.RegWrite(RegWrite),.SEControl(
		SEControl));


endmodule
