-- Vhdl test bench created from schematic c:\xilinx\csse\alu\x16bitalu.sch - Fri Feb 13 17:40:26 2004
--
-- Notes: 
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the 
-- stimulus for your design.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavioral OF testbench IS 

   COMPONENT x16bitalu
   PORT( bInvert	:	IN	STD_LOGIC; 
          co	:	OUT	STD_LOGIC; 
          a	:	IN	STD_LOGIC_VECTOR (15 DOWNTO 0); 
          b	:	IN	STD_LOGIC_VECTOR (15 DOWNTO 0); 
          Operation	:	IN	STD_LOGIC_VECTOR (1 DOWNTO 0); 
          Result	:	OUT	STD_LOGIC_VECTOR (15 DOWNTO 0); 
          Zero	:	OUT	STD_LOGIC; 
          cin	:	IN	STD_LOGIC);
   END COMPONENT;

   SIGNAL bInvert	:	STD_LOGIC;
   SIGNAL co	:	STD_LOGIC;
   SIGNAL a	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
   SIGNAL b	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
   SIGNAL Operation	:	STD_LOGIC_VECTOR (1 DOWNTO 0);
   SIGNAL Result	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
   SIGNAL Zero	:	STD_LOGIC;
   SIGNAL cin	:	STD_LOGIC;

BEGIN

   UUT: x16bitalu PORT MAP(
		bInvert => bInvert, 
		co => co, 
		a => a, 
		b => b, 
		Operation => Operation, 
		Result => Result, 
		Zero => Zero, 
		cin => cin
   );

-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN
      WAIT; -- will wait forever
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;
