library verilog;
use verilog.vl_types.all;
entity cancat2 is
    port(
        b               : in     vl_logic_vector(7 downto 0);
        irin            : in     vl_logic_vector(7 downto 0);
        lineout         : out    vl_logic_vector(15 downto 0)
    );
end cancat2;
