library verilog;
use verilog.vl_types.all;
entity acc16_mxilinx_bitadder is
    port(
        add             : in     vl_logic;
        b               : in     vl_logic_vector(15 downto 0);
        c               : in     vl_logic;
        ce              : in     vl_logic;
        ci              : in     vl_logic;
        d               : in     vl_logic_vector(15 downto 0);
        l               : in     vl_logic;
        r               : in     vl_logic;
        co              : out    vl_logic;
        ofl             : out    vl_logic;
        q               : out    vl_logic_vector(15 downto 0)
    );
end acc16_mxilinx_bitadder;
