// Verilog model created from C:\Xilinx\spartan2\data\drawing\nor16.sch - Thu Feb 12 22:10:46 2004

`timescale 1ns / 1ps

module NOR16_MXILINX_x16bitalu(I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10,
      I11, I12, I13, I14, I15, O);

    input I0;
    input I1;
    input I2;
    input I3;
    input I4;
    input I5;
    input I6;
    input I7;
    input I8;
    input I9;
    input I10;
    input I11;
    input I12;
    input I13;
    input I14;
    input I15;
   output O;
   
   wire CIN;
   wire C0;
   wire C1;
   wire C2;
   wire S0;
   wire S1;
   wire S2;
   wire S3;
   wire XLXN_1;
   
   MUXCY_L I_36_2 (.CI(CIN), .DI(XLXN_1), .S(S0), .LO(C0));
   // synthesis attribute RLOC of I_36_2 is "R1C0.S1"
   FMAP I_36_29 (.I1(I0), .I2(I1), .I3(I2), .I4(I3), .O(S0));
   // synthesis attribute RLOC of I_36_29 is "R1C0.S1"
   VCC I_36_107 (.P(CIN));
   GND I_36_109 (.G(XLXN_1));
   NOR4 I_36_110 (.I0(I0), .I1(I1), .I2(I2), .I3(I3), .O(S0));
   NOR4 I_36_127 (.I0(I4), .I1(I5), .I2(I6), .I3(I7), .O(S1));
   MUXCY_L I_36_129 (.CI(C0), .DI(XLXN_1), .S(S1), .LO(C1));
   // synthesis attribute RLOC of I_36_129 is "R1C0.S1"
   FMAP I_36_138 (.I1(I4), .I2(I5), .I3(I6), .I4(I7), .O(S1));
   // synthesis attribute RLOC of I_36_138 is "R1C0.S1"
   FMAP I_36_142 (.I1(I8), .I2(I9), .I3(I10), .I4(I11), .O(S2));
   // synthesis attribute RLOC of I_36_142 is "R0C0.S1"
   MUXCY_L I_36_147 (.CI(C1), .DI(XLXN_1), .S(S2), .LO(C2));
   // synthesis attribute RLOC of I_36_147 is "R0C0.S1"
   NOR4 I_36_151 (.I0(I8), .I1(I9), .I2(I10), .I3(I11), .O(S2));
   NOR4 I_36_161 (.I0(I12), .I1(I13), .I2(I14), .I3(I15), .O(S3));
   MUXCY I_36_165 (.CI(C2), .DI(XLXN_1), .S(S3), .O(O));
   // synthesis attribute RLOC of I_36_165 is "R0C0.S1"
   FMAP I_36_170 (.I1(I12), .I2(I13), .I3(I14), .I4(I15), .O(S3));
   // synthesis attribute RLOC of I_36_170 is "R0C0.S1"
endmodule
// Verilog model created from c:\xilinx\csse\alu\x16bitalu.sch - Thu Feb 12 22:10:46 2004

`timescale 1ns / 1ps

module x16bitalu(a, b, bInvert, cin, Operation, co, Result, Zero);

    input [15:0] a;
    input [15:0] b;
    input bInvert;
    input cin;
    input [1:0] Operation;
   output co;
   output [15:0] Result;
   output Zero;
   
   wire ground;
   wire XLXN_8;
   wire XLXN_17;
   wire XLXN_25;
   wire XLXN_41;
   wire XLXN_49;
   wire XLXN_57;
   wire XLXN_73;
   wire XLXN_75;
   wire XLXN_81;
   wire XLXN_89;
   wire XLXN_105;
   wire XLXN_113;
   wire XLXN_121;
   wire XLXN_135;
   wire XLXN_140;
   wire XLXN_152;
   
   onebitalu XLXI_1 (.a(a[0]), .b(b[0]), .bInvert(bInvert), .ci(cin),
         .Operation0(Operation[0]), .Operation1(Operation[1]), .SLT(XLXN_135),
         .aADDb(), .co(XLXN_8), .Result(Result[0]));
   onebitalu XLXI_19 (.a(a[1]), .b(b[1]), .bInvert(bInvert), .ci(XLXN_8),
         .Operation0(Operation[0]), .Operation1(Operation[1]), .SLT(ground),
         .aADDb(), .co(XLXN_17), .Result(Result[1]));
   onebitalu XLXI_20 (.a(a[2]), .b(b[2]), .bInvert(bInvert), .ci(XLXN_17),
         .Operation0(Operation[0]), .Operation1(Operation[1]), .SLT(ground),
         .aADDb(), .co(XLXN_25), .Result(Result[2]));
   onebitalu XLXI_21 (.a(a[3]), .b(b[3]), .bInvert(bInvert), .ci(XLXN_25),
         .Operation0(Operation[0]), .Operation1(Operation[1]), .SLT(ground),
         .aADDb(), .co(XLXN_140), .Result(Result[3]));
   onebitalu XLXI_22 (.a(a[4]), .b(b[4]), .bInvert(bInvert), .ci(XLXN_140),
         .Operation0(Operation[0]), .Operation1(Operation[1]), .SLT(ground),
         .aADDb(), .co(XLXN_41), .Result(Result[4]));
   onebitalu XLXI_23 (.a(a[5]), .b(b[5]), .bInvert(bInvert), .ci(XLXN_41),
         .Operation0(Operation[0]), .Operation1(Operation[1]), .SLT(ground),
         .aADDb(), .co(XLXN_49), .Result(Result[5]));
   onebitalu XLXI_24 (.a(a[6]), .b(b[6]), .bInvert(bInvert), .ci(XLXN_49),
         .Operation0(Operation[0]), .Operation1(Operation[1]), .SLT(ground),
         .aADDb(), .co(XLXN_57), .Result(Result[6]));
   onebitalu XLXI_25 (.a(a[7]), .b(b[7]), .bInvert(bInvert), .ci(XLXN_57),
         .Operation0(Operation[0]), .Operation1(Operation[1]), .SLT(ground),
         .aADDb(), .co(XLXN_75), .Result(Result[7]));
   onebitalu XLXI_26 (.a(a[8]), .b(b[8]), .bInvert(bInvert), .ci(XLXN_75),
         .Operation0(Operation[0]), .Operation1(Operation[1]), .SLT(ground),
         .aADDb(), .co(XLXN_73), .Result(Result[8]));
   onebitalu XLXI_27 (.a(a[9]), .b(b[9]), .bInvert(bInvert), .ci(XLXN_73),
         .Operation0(Operation[0]), .Operation1(Operation[1]), .SLT(ground),
         .aADDb(), .co(XLXN_81), .Result(Result[9]));
   onebitalu XLXI_28 (.a(a[10]), .b(b[10]), .bInvert(bInvert), .ci(XLXN_81),
         .Operation0(Operation[0]), .Operation1(Operation[1]), .SLT(ground),
         .aADDb(), .co(XLXN_89), .Result(Result[10]));
   onebitalu XLXI_29 (.a(a[11]), .b(b[11]), .bInvert(bInvert), .ci(XLXN_89),
         .Operation0(Operation[0]), .Operation1(Operation[1]), .SLT(ground),
         .aADDb(), .co(XLXN_152), .Result(Result[11]));
   onebitalu XLXI_30 (.a(a[12]), .b(b[12]), .bInvert(bInvert), .ci(XLXN_152),
         .Operation0(Operation[0]), .Operation1(Operation[1]), .SLT(ground),
         .aADDb(), .co(XLXN_105), .Result(Result[12]));
   onebitalu XLXI_31 (.a(a[13]), .b(b[13]), .bInvert(bInvert), .ci(XLXN_105),
         .Operation0(Operation[0]), .Operation1(Operation[1]), .SLT(ground),
         .aADDb(), .co(XLXN_113), .Result(Result[13]));
   onebitalu XLXI_32 (.a(a[14]), .b(b[14]), .bInvert(bInvert), .ci(XLXN_113),
         .Operation0(Operation[0]), .Operation1(Operation[1]), .SLT(ground),
         .aADDb(), .co(XLXN_121), .Result(Result[14]));
   onebitalu XLXI_33 (.a(a[15]), .b(b[15]), .bInvert(bInvert), .ci(XLXN_121),
         .Operation0(Operation[0]), .Operation1(Operation[1]), .SLT(ground),
         .aADDb(XLXN_135), .co(co), .Result(Result[15]));
   NOR16_MXILINX_x16bitalu XLXI_34 (.I0(Result[15]), .I1(Result[14]),
         .I2(Result[13]), .I3(Result[12]), .I4(Result[11]), .I5(Result[10]),
         .I6(Result[9]), .I7(Result[8]), .I8(Result[7]), .I9(Result[6]),
         .I10(Result[5]), .I11(Result[4]), .I12(Result[3]), .I13(Result[2]),
         .I14(Result[1]), .I15(Result[0]), .O(Zero));
   // synthesis attribute HU_SET of XLXI_34 is "XLXI_34_0"
   GND XLXI_35 (.G(ground));
endmodule
