library verilog;
use verilog.vl_types.all;
entity cancat is
    port(
        pcin            : in     vl_logic_vector(3 downto 0);
        irin            : in     vl_logic_vector(11 downto 0);
        jumpout         : out    vl_logic_vector(15 downto 0)
    );
end cancat;
