module Mux4(mux_out, data0,data1,data2,data3, controlin);

output [15:0] mux_out;
input [15:0] data0;
input [15:0] data1;
input [15:0] data2;
input [15:0] data3;
input [1:0] controlin;

reg [15:0] mux_out;

always @ (mux_out, data0, data1,data2,data3, controlin)

		case(controlin)
				
				0:	mux_out <= data0;
				1:	mux_out <= data1;
				2:	mux_out <= data2;
				3:	mux_out <= data3;
				default: mux_out <=16'bx;
		endcase
endmodule