library verilog;
use verilog.vl_types.all;
entity x16bitalu is
    port(
        a               : in     vl_logic_vector(15 downto 0);
        b               : in     vl_logic_vector(15 downto 0);
        binvert         : in     vl_logic;
        cin             : in     vl_logic;
        operation       : in     vl_logic_vector(1 downto 0);
        co              : out    vl_logic;
        result          : out    vl_logic_vector(15 downto 0);
        zero            : out    vl_logic
    );
end x16bitalu;
