library verilog;
use verilog.vl_types.all;
entity control is
    port(
        aluop           : out    vl_logic_vector(1 downto 0);
        alusrcb         : out    vl_logic_vector(1 downto 0);
        ir              : in     vl_logic_vector(15 downto 0);
        memtoreg        : out    vl_logic_vector(2 downto 0);
        pcsource        : out    vl_logic_vector(2 downto 0);
        regdst          : out    vl_logic_vector(1 downto 0);
        clk             : in     vl_logic;
        ctrlinterrupt   : in     vl_logic;
        reset           : in     vl_logic;
        check           : out    vl_logic;
        epcwrite        : out    vl_logic;
        iebclear        : out    vl_logic;
        iebcontrol      : out    vl_logic;
        iord            : out    vl_logic;
        irwrite         : out    vl_logic;
        memread         : out    vl_logic;
        memwrite        : out    vl_logic;
        pcwrite         : out    vl_logic;
        pcwritecond     : out    vl_logic;
        portwrite       : out    vl_logic;
        regbcontrol     : out    vl_logic;
        regwrite        : out    vl_logic;
        secontrol       : out    vl_logic
    );
end control;
