Release 5.2.03i - xst F.31
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.68 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: zerochecker.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Low Level Synthesis
  6) Final Report
     6.1) Device utilization summary
     6.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : zerochecker.prj
Input Format                       : VERILOG
Ignore Synthesis Constraint File   : NO
Verilog Search Path                : 
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : zerochecker
Output Format                      : NGC
Target Device                      : xc2s50e-6pq208

---- Source Options
Top Module Name                    : zerochecker
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Top module area constraint         : 100
Top module allowed area overflow   : 5

---- Other Options
read_cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "zerochecker.prj"
Compiling include file "zerochecker.v"
Module <zerochecker> compiled
Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"
No errors in compilation

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analysis of file <zerochecker.prj> succeeded.
 
WARNING:Xst:878 - zerochecker.v line 100: Unrecognized directive. Ignoring.
 
Analyzing top module <zerochecker>.
Module <zerochecker> is correct for synthesis.
WARNING:Xst:37 - Unknown property "fpga_dont_touch".

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <zerochecker>.
    Related source file is zerochecker.v.
WARNING:Xst:1306 - Output <A_EQ_B> is never assigned.
WARNING:Xst:647 - Input <A<15>> is never used.
WARNING:Xst:647 - Input <A<14>> is never used.
WARNING:Xst:647 - Input <A<13>> is never used.
WARNING:Xst:647 - Input <A<12>> is never used.
WARNING:Xst:647 - Input <A<11>> is never used.
WARNING:Xst:647 - Input <A<10>> is never used.
WARNING:Xst:647 - Input <A<9>> is never used.
WARNING:Xst:647 - Input <A<8>> is never used.
WARNING:Xst:647 - Input <A<7>> is never used.
WARNING:Xst:647 - Input <A<6>> is never used.
WARNING:Xst:647 - Input <A<5>> is never used.
WARNING:Xst:647 - Input <A<4>> is never used.
WARNING:Xst:647 - Input <A<3>> is never used.
WARNING:Xst:647 - Input <A<2>> is never used.
WARNING:Xst:647 - Input <A<1>> is never used.
WARNING:Xst:647 - Input <A<0>> is never used.
Unit <zerochecker> synthesized.


=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "C:/Xilinx/data/librtl.xst" Consulted

Optimizing unit <zerochecker> ...

Mapping all equations...
Loading device for application Xst from file '2s50e.nph' in environment C:/Xilinx.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block zerochecker, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : zerochecker.ngr
Top Level Output File Name         : zerochecker
Output Format                      : NGC
Optimization Criterion             : Speed
Keep Hierarchy                     : NO
Macro Generator                    : macro+

Design Statistics
# IOs                              : 17

Cell Usage :
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50epq208-6 



=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
CPU : 2.10 / 3.01 s | Elapsed : 2.00 / 3.00 s
 
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Total memory usage is 60664 kilobytes


