# Verilog : PDCL (jhdparse)
__projnav/zerochecker_jhdparse_tcl.rsp
# ProjNav -> New Source -> TBW
__projnav\hb_cmds
# ModelSim : Simulate Behavioral Verilog Model
__projnav/zerochecker_tb_createfdo.rsp
zerochecker_tb.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Verilog : Create Schematic Symbol
__projnav/jhdparse.log
# xst flow : RunXST
zerochecker.syr
zerochecker.ngr
zerochecker.prj
zerochecker.sprj
zerochecker.ana
zerochecker.stx
zerochecker.cmd_log
zerochecker.ngc
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
c:\xilinx\projects\zerochecker/_ngo
zerochecker.ngd
zerochecker_ngdbuild.nav
zerochecker.bld
.untf
zerochecker.cmd_log
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
c:\xilinx\projects\zerochecker/_ngo
zerochecker.ngd
zerochecker_ngdbuild.nav
zerochecker.bld
.untf
zerochecker.cmd_log
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
c:\xilinx\projects\zerochecker/_ngo
zerochecker.ngd
zerochecker_ngdbuild.nav
zerochecker.bld
.untf
zerochecker.cmd_log
