Release 5.2.03i - xst F.31
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
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CPU : 0.00 / 0.36 s | Elapsed : 0.00 / 0.00 s
 
--> Reading design: constate.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Low Level Synthesis
  6) Final Report
     6.1) Device utilization summary
     6.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : constate.prj
Input Format                       : VERILOG
Ignore Synthesis Constraint File   : NO
Verilog Search Path                : 
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : constate
Output Format                      : NGC
Target Device                      : xc2s200e-6pq208

---- Source Options
Top Module Name                    : constate
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Top module area constraint         : 100
Top module allowed area overflow   : 5

---- Other Options
read_cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "constate.prj"
Compiling include file "CONSTATE.v"
Module <constate> compiled
Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"
No errors in compilation

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analysis of file <constate.prj> succeeded.
 
 
Analyzing top module <constate>.
Module <constate> is correct for synthesis.
WARNING:Xst:39 - Property "BOX_TYPE" not applicable on a signal.
WARNING:Xst:39 - Property "BOX_TYPE" not applicable on a signal.
WARNING:Xst:39 - Property "BOX_TYPE" not applicable on a signal.
WARNING:Xst:39 - Property "BOX_TYPE" not applicable on a signal.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <constate>.
    Related source file is CONSTATE.v.
    Found 1-bit register for signal <add3>.
    Found 1-bit register for signal <add4>.
    Found 1-bit register for signal <and3>.
    Found 1-bit register for signal <and4>.
    Found 1-bit register for signal <b3>.
    Found 1-bit register for signal <b4>.
    Found 1-bit register for signal <BP_ALUOp0>.
    Found 1-bit register for signal <BP_ALUOp1>.
    Found 1-bit register for signal <BP_ALUOp2>.
    Found 1-bit register for signal <BP_EPCWRITE>.
    Found 1-bit register for signal <BP_INTWRITE>.
    Found 1-bit register for signal <BP_IRWRITE>.
    Found 1-bit register for signal <BP_MEMWRITE>.
    Found 1-bit register for signal <BP_Mux0>.
    Found 1-bit register for signal <BP_Mux10>.
    Found 1-bit register for signal <BP_Mux1b0>.
    Found 1-bit register for signal <BP_Mux1b1>.
    Found 1-bit register for signal <BP_Mux1b2>.
    Found 1-bit register for signal <BP_Mux2>.
    Found 1-bit register for signal <BP_Mux3b0>.
    Found 1-bit register for signal <BP_Mux3b1>.
    Found 1-bit register for signal <BP_Mux5>.
    Found 1-bit register for signal <BP_Mux6b0>.
    Found 1-bit register for signal <BP_Mux6b1>.
    Found 1-bit register for signal <BP_Mux6b2>.
    Found 1-bit register for signal <BP_Mux7b0>.
    Found 1-bit register for signal <BP_Mux7b1>.
    Found 1-bit register for signal <BP_Mux7b2>.
    Found 1-bit register for signal <BP_Mux8b0>.
    Found 1-bit register for signal <BP_Mux8b1>.
    Found 1-bit register for signal <BP_Mux9>.
    Found 1-bit register for signal <BP_OUTWRITE>.
    Found 1-bit register for signal <BP_PCWRITE>.
    Found 1-bit register for signal <BP_REGWRITE>.
    Found 1-bit register for signal <BP_SPECIALWRITE>.
    Found 1-bit register for signal <INT_STATE>.
    Found 1-bit register for signal <inv3>.
    Found 1-bit register for signal <inv4>.
    Found 1-bit register for signal <jal3>.
    Found 1-bit register for signal <jr3>.
    Found 1-bit register for signal <lds3>.
    Found 1-bit register for signal <lli3>.
    Found 1-bit register for signal <lli4>.
    Found 1-bit register for signal <lui3>.
    Found 1-bit register for signal <lw3>.
    Found 1-bit register for signal <lw4>.
    Found 1-bit register for signal <or3>.
    Found 1-bit register for signal <or4>.
    Found 1-bit register for signal <seq3>.
    Found 1-bit register for signal <seq4a>.
    Found 1-bit register for signal <seq4b>.
    Found 1-bit register for signal <sll3>.
    Found 1-bit register for signal <slt3>.
    Found 1-bit register for signal <slt4>.
    Found 1-bit register for signal <spc3>.
    Found 1-bit register for signal <STATE0>.
    Found 1-bit register for signal <STATE1>.
    Found 1-bit register for signal <sub3>.
    Found 1-bit register for signal <sub4>.
    Found 1-bit register for signal <sw3>.
    Summary:
	inferred  60 D-type flip-flop(s).
Unit <constate> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 60
  1-bit register                   : 60

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "C:/Xilinx/data/librtl.xst" Consulted

Optimizing unit <constate> ...

Mapping all equations...
Loading device for application Xst from file '2s200e.nph' in environment C:/Xilinx.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block constate, actual ratio is 3.
FlipFlop STATE1 has been replicated 2 time(s)
FlipFlop STATE0 has been replicated 1 time(s)
FlipFlop b3 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : constate.ngr
Top Level Output File Name         : constate
Output Format                      : NGC
Optimization Criterion             : Speed
Keep Hierarchy                     : NO
Macro Generator                    : macro+

Design Statistics
# IOs                              : 41

Macro Statistics :
# Registers                        : 60
#      1-bit register              : 60

Cell Usage :
# BELS                             : 221
#      LUT2                        : 29
#      LUT2_D                      : 3
#      LUT2_L                      : 4
#      LUT3                        : 29
#      LUT3_D                      : 1
#      LUT3_L                      : 7
#      LUT4                        : 83
#      LUT4_D                      : 5
#      LUT4_L                      : 56
#      MUXF5                       : 3
#      VCC                         : 1
# FlipFlops/Latches                : 64
#      FDC                         : 58
#      FDP                         : 6
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 40
#      IBUF                        : 11
#      OBUF                        : 29
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200epq208-6 

 Number of Slices:                     124  out of   2352     5%  
 Number of Slice Flip Flops:            64  out of   4704     1%  
 Number of 4 input LUTs:               217  out of   4704     4%  
 Number of bonded IOBs:                 40  out of    146    27%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 64    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 8.323ns (Maximum Frequency: 120.149MHz)
   Minimum input arrival time before clock: 13.833ns
   Maximum output required time after clock: 6.778ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'CLK'
Delay:               8.323ns (Levels of Logic = 4)
  Source:            STATE1
  Destination:       BP_Mux8b1
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: STATE1 to BP_Mux8b1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             21   0.992   2.600  STATE1 (STATE1)
     LUT4:I3->O            1   0.468   0.920  Ker417415 (CHOICE3933)
     LUT4:I3->O            1   0.468   0.000  Ker4174271_G (N30110)
     MUXF5:I1->O           4   0.403   1.280  Ker4174271 (CHOICE3937)
     LUT4_L:I0->LO         1   0.468   0.000  _n004554 (_n0045)
     FDC:D                     0.724          BP_Mux8b1
    ----------------------------------------
    Total                      8.323ns (3.523ns logic, 4.800ns route)
                                       (42.3% logic, 57.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
Offset:              13.833ns (Levels of Logic = 8)
  Source:            OPCODE2
  Destination:       BP_PCWRITE
  Destination Clock: CLK rising

  Data Path: OPCODE2 to BP_PCWRITE
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            46   0.797   3.600  OPCODE2_IBUF (OPCODE2_IBUF)
     LUT2:I0->O            5   0.468   1.392  Ker42431 (N4245)
     LUT3:I0->O            3   0.468   1.184  Ker39511 (N3953)
     LUT2:I0->O            1   0.468   0.920  _n004934 (CHOICE3838)
     LUT3:I0->O            1   0.468   0.920  _n004941_SW0 (N29839)
     LUT4_L:I1->LO         1   0.468   0.100  _n004941 (CHOICE3841)
     LUT4:I0->O            1   0.468   0.920  _n004944 (CHOICE3842)
     LUT2_L:I1->LO         1   0.468   0.000  _n004950 (_n0049)
     FDP:D                     0.724          BP_PCWRITE
    ----------------------------------------
    Total                     13.833ns (4.797ns logic, 9.036ns route)
                                       (34.7% logic, 65.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
Offset:              6.778ns (Levels of Logic = 1)
  Source:            BP_SPECIALWRITE
  Destination:       SPECIALWRITE
  Source Clock:      CLK rising

  Data Path: BP_SPECIALWRITE to SPECIALWRITE
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.992   1.184  BP_SPECIALWRITE (BP_SPECIALWRITE)
     OBUF:I->O                 4.602          SPECIALWRITE_OBUF (SPECIALWRITE)
    ----------------------------------------
    Total                      6.778ns (5.594ns logic, 1.184ns route)
                                       (82.5% logic, 17.5% route)

=========================================================================
CPU : 12.72 / 13.27 s | Elapsed : 12.00 / 13.00 s
 
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Total memory usage is 80696 kilobytes


