# Schematic : PDCL (jhdparse)
# Verilog : PDCL (jhdparse)
__projnav/CONSTATE_jhdparse_tcl.rsp
# Verilog : Create Schematic Symbol
__projnav/jhdparse.log
# xst flow : RunXST
constate.syr
constate.ngr
constate.prj
constate.sprj
constate.ana
constate.stx
constate.cmd_log
constate.ngc
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
c:\xilinx\projects\controlunit/_ngo
constate.ngd
constate_ngdbuild.nav
constate.bld
.untf
constate.cmd_log
# Implementation : Map
constate.nc1
constate.mrp
constate.pcf
constate.ngm
constate_map.ngm
constate.mdf
constate_map.ncd
__projnav/map.log
constate.cmd_log
# ProjNav -> New Source -> TBW
__projnav\hb_cmds
# ProjNav -> New Source -> TBW
__projnav\hb_cmds
# ModelSim : Simulate Behavioral Verilog Model
__projnav/constate_tb_createfdo.rsp
constate_tb.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
