library verilog;
use verilog.vl_types.all;
entity constate is
    port(
        \CLK\           : in     vl_logic;
        \FUNCT0\        : in     vl_logic;
        \FUNCT1\        : in     vl_logic;
        \FUNCT2\        : in     vl_logic;
        \FUNCT3\        : in     vl_logic;
        \INTERRUPT\     : in     vl_logic;
        \OPCODE0\       : in     vl_logic;
        \OPCODE1\       : in     vl_logic;
        \OPCODE2\       : in     vl_logic;
        \OPCODE3\       : in     vl_logic;
        \RESET\         : in     vl_logic;
        \ZCValue\       : in     vl_logic;
        \ALUOp0\        : out    vl_logic;
        \ALUOp1\        : out    vl_logic;
        \ALUOp2\        : out    vl_logic;
        \EPCWRITE\      : out    vl_logic;
        \INTWRITE\      : out    vl_logic;
        \IRWRITE\       : out    vl_logic;
        \MEMWRITE\      : out    vl_logic;
        \Mux0\          : out    vl_logic;
        \Mux1b0\        : out    vl_logic;
        \Mux1b1\        : out    vl_logic;
        \Mux1b2\        : out    vl_logic;
        \Mux2\          : out    vl_logic;
        \Mux3b0\        : out    vl_logic;
        \Mux3b1\        : out    vl_logic;
        \Mux5\          : out    vl_logic;
        \Mux6b0\        : out    vl_logic;
        \Mux6b1\        : out    vl_logic;
        \Mux6b2\        : out    vl_logic;
        \Mux7b0\        : out    vl_logic;
        \Mux7b1\        : out    vl_logic;
        \Mux7b2\        : out    vl_logic;
        \Mux8b0\        : out    vl_logic;
        \Mux8b1\        : out    vl_logic;
        \Mux9\          : out    vl_logic;
        \Mux10\         : out    vl_logic;
        \OUTWRITE\      : out    vl_logic;
        \PCWRITE\       : out    vl_logic;
        \REGWRITE\      : out    vl_logic;
        \SPECIALWRITE\  : out    vl_logic
    );
end constate;
