library verilog;
use verilog.vl_types.all;
entity concatanation is
    port(
        \PCIn\          : in     vl_logic_vector(2 downto 0);
        \JumpIn\        : in     vl_logic_vector(12 downto 0);
        output16        : out    vl_logic_vector(15 downto 0)
    );
end concatanation;
