// C:\XILINX\PROJECTS\CONCATANATION
// Verilog Annotation Test Bench created by
// HDL Bencher 5.1i
// Fri Oct 31 22:44:32 2003

`timescale 1ns/1ns

`define ADDR_SZ	4
`define RAM_B_UPPER	30
`define RAM_C_UPPER	50
`define RAM_B_LOWER	20
`define RAM_WIDTH	16
`define RAM_A_LOWER	0
`define RAM_C_LOWER	40
`define RAM_A_UPPER	10
`define REG_WIDTH	16

module testbench;
	reg [2:0] PCIn;
	reg [12:0] JumpIn;
	wire [15:0] output16;

	concatanation UUT (
		.PCIn(PCIn),
		.JumpIn(JumpIn),
		.output16(output16)
	);

	integer TX_FILE;
	integer TX_ERROR;

always begin // Annotate outputs process
	#50
	ANNOTATE_output16;
	#50
	 begin end //null command
end

initial
begin
	TX_ERROR=0;
	TX_FILE=$fopen("c:\\xilinx\\projects\\concatanation\\concatanation_tb.ano");

	// --------------------
	PCIn = 3'b000; //0
	JumpIn = 13'b0000000000000; //0
	// --------------------
	#100 // Time=100 ns
	PCIn = 3'b001; //1
	// --------------------
	#100 // Time=200 ns
	PCIn = 3'b010; //2
	JumpIn = 13'b0000000000001; //1
	// --------------------
	#100 // Time=300 ns
	PCIn = 3'b011; //3
	// --------------------
	#100 // Time=400 ns
	PCIn = 3'b100; //4
	JumpIn = 13'b0000000000010; //2
	// --------------------
	#100 // Time=500 ns
	PCIn = 3'b101; //5
	// --------------------
	#100 // Time=600 ns
	PCIn = 3'b110; //6
	JumpIn = 13'b0000000000011; //3
	// --------------------
	#100 // Time=700 ns
	PCIn = 3'b111; //7
	// --------------------
	#100 // Time=800 ns
	JumpIn = 13'b0000000000100; //4
	// --------------------
	#150 // Time=950 ns
	// --------------------

	begin
		$display("Success! Annotation Simulation Complete.");
		$fdisplay(TX_FILE,"Total[%d]",TX_ERROR);
	end

	$fclose(TX_FILE);
	$stop;

end

task ANNOTATE_output16;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,output16,%b]",
			$time, output16);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

endmodule
