library verilog;
use verilog.vl_types.all;
entity \SPCLogic\ is
    port(
        \IR\            : in     vl_logic_vector(3 downto 0);
        \SPCWrite\      : in     vl_logic_vector(3 downto 0);
        \EPCWrite\      : out    vl_logic;
        \INTWrite\      : out    vl_logic;
        \OutWrite\      : out    vl_logic
    );
end \SPCLogic\;
