Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning    SPCLogic.v
Writing SPCLogic.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning    SPCLogic.v
Writing SPCLogic.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "SPCLogic.prj"
Compiling include file "SPCLogic.v"
Module <SPCLogic> compiled
ERROR:HDLCompilers:26 - SPCLogic.v line 7 expecting 'endmodule', found 'if'
Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"
Analysis of file <SPCLogic.prj> failed.
CPU : 0.53 / 1.41 s | Elapsed : 1.00 / 1.00 s
 
--> 

Total memory usage is 43136 kilobytes


Error: XST failed
Reason: 

Completed process "Synthesize".


Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning    SPCLogic.v
Writing SPCLogic.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "SPCLogic.prj"
Compiling include file "SPCLogic.v"
Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"
Module <SPCLogic> compiled
ERROR:HDLCompilers:42 - SPCLogic.v line 11 Illegal LHS of procedural continuous assignment
ERROR:HDLCompilers:42 - SPCLogic.v line 13 Illegal LHS of procedural continuous assignment
ERROR:HDLCompilers:42 - SPCLogic.v line 15 Illegal LHS of procedural continuous assignment
Analysis of file <SPCLogic.prj> failed.
CPU : 0.62 / 1.14 s | Elapsed : 1.00 / 1.00 s
 
--> 

Total memory usage is 53376 kilobytes


Error: XST failed
Reason: 

Completed process "Synthesize".


Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning    SPCLogic.v
Writing SPCLogic.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning    SPCLogic.v
Writing SPCLogic.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "SPCLogic.prj"
Compiling include file "SPCLogic.v"
Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"
Module <SPCLogic> compiled
ERROR:HDLCompilers:42 - SPCLogic.v line 15 Illegal LHS of procedural continuous assignment
ERROR:HDLCompilers:42 - SPCLogic.v line 17 Illegal LHS of procedural continuous assignment
ERROR:HDLCompilers:42 - SPCLogic.v line 19 Illegal LHS of procedural continuous assignment
Analysis of file <SPCLogic.prj> failed.
CPU : 0.60 / 1.17 s | Elapsed : 0.00 / 1.00 s
 
--> 

Total memory usage is 53376 kilobytes


Error: XST failed
Reason: 

Completed process "Synthesize".


Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning    SPCLogic.v
Writing SPCLogic.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "SPCLogic.prj"
Compiling include file "SPCLogic.v"
Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"
Module <SPCLogic> compiled
ERROR:HDLCompilers:42 - SPCLogic.v line 15 Illegal LHS of procedural continuous assignment
ERROR:HDLCompilers:42 - SPCLogic.v line 17 Illegal LHS of procedural continuous assignment
ERROR:HDLCompilers:42 - SPCLogic.v line 19 Illegal LHS of procedural continuous assignment
Analysis of file <SPCLogic.prj> failed.
CPU : 0.61 / 1.22 s | Elapsed : 1.00 / 1.00 s
 
--> 

Total memory usage is 53376 kilobytes


Error: XST failed
Reason: 

Completed process "Synthesize".


Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning    SPCLogic.v
Writing SPCLogic.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "SPCLogic.prj"
Compiling include file "SPCLogic.v"
Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"
Module <SPCLogic> compiled
ERROR:HDLCompilers:44 - SPCLogic.v line 15 Illegal LHS of blocking assignment
ERROR:HDLCompilers:44 - SPCLogic.v line 17 Illegal LHS of blocking assignment
ERROR:HDLCompilers:44 - SPCLogic.v line 19 Illegal LHS of blocking assignment
Analysis of file <SPCLogic.prj> failed.
CPU : 0.75 / 1.29 s | Elapsed : 1.00 / 2.00 s
 
--> 

Total memory usage is 52352 kilobytes


Error: XST failed
Reason: 

Completed process "Synthesize".


Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning    SPCLogic.v
Writing SPCLogic.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning    SPCLogic.v
Writing SPCLogic.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "SPCLogic.prj"
Compiling include file "SPCLogic.v"
Module <SPCLogic> compiled
Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"
ERROR:HDLCompilers:44 - SPCLogic.v line 15 Illegal LHS of blocking assignment
ERROR:HDLCompilers:44 - SPCLogic.v line 17 Illegal LHS of blocking assignment
ERROR:HDLCompilers:44 - SPCLogic.v line 19 Illegal LHS of blocking assignment
Analysis of file <SPCLogic.prj> failed.
CPU : 0.71 / 1.46 s | Elapsed : 1.00 / 1.00 s
 
--> 

Total memory usage is 53376 kilobytes


Error: XST failed
Reason: 

Completed process "Synthesize".


Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning    SPCLogic.v
Writing SPCLogic.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning    SPCLogic.v
Writing SPCLogic.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    SPCLogic.v
No errors or warnings

JHDPARSE complete -    0 errors,    0 warnings.


Release 5.2.03i - spl2sym F.31
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "SPCLogic.prj"
Compiling include file "SPCLogic.v"
Module <SPCLogic> compiled
Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"
ERROR:HDLCompilers:42 - SPCLogic.v line 15 Illegal LHS of procedural continuous assignment
ERROR:HDLCompilers:42 - SPCLogic.v line 17 Illegal LHS of procedural continuous assignment
ERROR:HDLCompilers:42 - SPCLogic.v line 19 Illegal LHS of procedural continuous assignment
Analysis of file <SPCLogic.prj> failed.
CPU : 0.66 / 1.23 s | Elapsed : 1.00 / 1.00 s
 
--> 

Total memory usage is 53376 kilobytes


Error: XST failed
Reason: 

Completed process "Synthesize".


Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning    SPCLogic.v
Writing SPCLogic.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "SPCLogic.prj"
Compiling include file "SPCLogic.v"
Module <SPCLogic> compiled
Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"
No errors in compilation

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analysis of file <SPCLogic.prj> succeeded.
 
 
Analyzing top module <SPCLogic>.
WARNING:Xst:905 - SPCLogic.v line 13: The signals <IR> are missing in the sensitivity list of always block.
Module <SPCLogic> is correct for synthesis.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <SPCLogic>.
    Related source file is SPCLogic.v.
WARNING:Xst:647 - Input <SPCWrite<3>> is never used.
WARNING:Xst:647 - Input <SPCWrite<2>> is never used.
WARNING:Xst:647 - Input <SPCWrite<1>> is never used.
WARNING:Xst:647 - Input <SPCWrite<0>> is never used.
WARNING:Xst:647 - Input <IR<3>> is never used.
WARNING:Xst:647 - Input <IR<2>> is never used.
WARNING:Xst:647 - Input <IR<1>> is never used.
WARNING:Xst:647 - Input <IR<0>> is never used.
Unit <SPCLogic> synthesized.


=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "C:/Xilinx/data/librtl.xst" Consulted

Optimizing unit <SPCLogic> ...

Mapping all equations...
Loading device for application Xst from file '2s200e.nph' in environment C:/Xilinx.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block SPCLogic, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200epq208-6 

 Number of bonded IOBs:                  3  out of    146     2%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: No path found

=========================================================================

Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning    SPCLogic.v
Writing SPCLogic.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning    SPCLogic.v
Writing SPCLogic.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "SPCLogic.prj"
Compiling include file "SPCLogic.v"
Module <SPCLogic> compiled
Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"
No errors in compilation

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analysis of file <SPCLogic.prj> succeeded.
 
 
Analyzing top module <SPCLogic>.
ERROR:Xst:1468 - SPCLogic.v line 11: Unexpected event in always block sensitivity list.
 
Found 1 error(s). Aborting synthesis.
CPU : 0.73 / 1.27 s | Elapsed : 1.00 / 1.00 s
 
--> 

Total memory usage is 54400 kilobytes


Error: XST failed
Reason: 

Completed process "Synthesize".


Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning    SPCLogic.v
Writing SPCLogic.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "SPCLogic.prj"
Compiling include file "SPCLogic.v"
Module <SPCLogic> compiled
Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"
No errors in compilation

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analysis of file <SPCLogic.prj> succeeded.
 
 
Analyzing top module <SPCLogic>.
ERROR:Xst:1468 - SPCLogic.v line 11: Unexpected event in always block sensitivity list.
 
Found 1 error(s). Aborting synthesis.
CPU : 0.74 / 1.33 s | Elapsed : 1.00 / 2.00 s
 
--> 

Total memory usage is 54400 kilobytes


Error: XST failed
Reason: 

Completed process "Synthesize".


Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning    SPCLogic.v
Writing SPCLogic.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning    SPCLogic.v
Writing SPCLogic.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning    SPCLogic.v
Writing SPCLogic.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning    SPCLogic.v
Writing SPCLogic.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning    SPCLogic.v
Writing SPCLogic.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    SPCLogic.v
No errors or warnings

JHDPARSE complete -    0 errors,    0 warnings.


Release 5.2.03i - spl2sym F.31
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "SPCLogic.prj"
Compiling include file "SPCLogic.v"
Module <SPCLogic> compiled
ERROR:HDLCompilers:26 - SPCLogic.v line 8 expecting 'endmodule', found 'if'
Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"
Analysis of file <SPCLogic.prj> failed.
CPU : 0.47 / 1.05 s | Elapsed : 0.00 / 1.00 s
 
--> 

Total memory usage is 43136 kilobytes


Error: XST failed
Reason: 

Completed process "Synthesize".


Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning    SPCLogic.v
Writing SPCLogic.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    SPCLogic.v
No errors or warnings

JHDPARSE complete -    0 errors,    0 warnings.


Release 5.2.03i - spl2sym F.31
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "SPCLogic.prj"
Compiling include file "SPCLogic.v"
ERROR:HDLCompilers:26 - SPCLogic.v line 8 unexpected token: '='
ERROR:HDLCompilers:26 - SPCLogic.v line 8 expecting ';', found ')'
ERROR:HDLCompilers:26 - SPCLogic.v line 9 unexpected token: '='
ERROR:HDLCompilers:26 - SPCLogic.v line 9 expecting ';', found ')'
ERROR:HDLCompilers:26 - SPCLogic.v line 10 unexpected token: '='
ERROR:HDLCompilers:26 - SPCLogic.v line 10 expecting ';', found ')'
Module <SPCLogic> compiled
Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"
Analysis of file <SPCLogic.prj> failed.
CPU : 0.47 / 0.97 s | Elapsed : 1.00 / 1.00 s
 
--> 

Total memory usage is 43136 kilobytes


Error: XST failed
Reason: 

Completed process "Synthesize".


Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning    SPCLogic.v
Writing SPCLogic.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    SPCLogic.v
No errors or warnings

JHDPARSE complete -    0 errors,    0 warnings.


Release 5.2.03i - spl2sym F.31
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "SPCLogic.prj"
Compiling include file "SPCLogic.v"
Module <SPCLogic> compiled
ERROR:HDLCompilers:26 - SPCLogic.v line 11 expecting 'endmodule', found 'end'
Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"
Analysis of file <SPCLogic.prj> failed.
CPU : 0.46 / 0.99 s | Elapsed : 1.00 / 1.00 s
 
--> 

Total memory usage is 43136 kilobytes


Error: XST failed
Reason: 

Completed process "Synthesize".


Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning    SPCLogic.v
Writing SPCLogic.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning    SPCLogic.v
Writing SPCLogic.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning    SPCLogic.v
Writing SPCLogic.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "SPCLogic.prj"
Compiling include file "SPCLogic.v"
Module <SPCLogic> compiled
Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"
No errors in compilation

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analysis of file <SPCLogic.prj> succeeded.
 
 
Analyzing top module <SPCLogic>.
Module <SPCLogic> is correct for synthesis.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <SPCLogic>.
    Related source file is SPCLogic.v.
Unit <SPCLogic> synthesized.


=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "C:/Xilinx/data/librtl.xst" Consulted

Optimizing unit <SPCLogic> ...

Mapping all equations...
Loading device for application Xst from file '2s200e.nph' in environment C:/Xilinx.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block SPCLogic, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200epq208-6 

 Number of Slices:                       3  out of   2352     0%  
 Number of 4 input LUTs:                 6  out of   4704     0%  
 Number of bonded IOBs:                 11  out of    146     7%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 9.359ns

=========================================================================

Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -quiet -dd c:\xilinx\projects\spclogic/_ngo -i -p
xc2s200e-pq208-6 SPCLogic.ngc SPCLogic.ngd 

Reading NGO file "C:/Xilinx/projects/SPCLogic/SPCLogic.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "SPCLogic.ngd" ...

Writing NGDBUILD log file "SPCLogic.bld"...

NGDBUILD done.

Completed process "Translate".



Started process "Map".

Using target part "2s200epq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of 4 input LUTs:             6 out of  4,704    1%
Logic Distribution:
    Number of occupied Slices:                           3 out of  2,352    1%
    Number of Slices containing only related logic:      3 out of      3  100%
    Number of Slices containing unrelated logic:         0 out of      3    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:         6 out of  4,704    1%
   Number of bonded IOBs:            11 out of    142    7%

Total equivalent gate count for design:  36
Additional JTAG gate count for IOBs:  528
Peak Memory Usage:  55 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "SPCLogic_map.mrp" for details.

Completed process "Map".

Mapping Module SPCLogic . . .
MAP command line:
map -quiet -p xc2s200e-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o SPCLogic_map.ncd SPCLogic.ngd SPCLogic.pcf
Mapping Module SPCLogic: DONE



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JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning    SPCLogic.v
Writing SPCLogic.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
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JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning    SPCLogic.v
Writing SPCLogic.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "SPCLogic.prj"
Compiling include file "SPCLogic.v"
Module <SPCLogic> compiled
Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"
No errors in compilation

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analysis of file <SPCLogic.prj> succeeded.
 
 
Analyzing top module <SPCLogic>.
Module <SPCLogic> is correct for synthesis.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <SPCLogic>.
    Related source file is SPCLogic.v.
Unit <SPCLogic> synthesized.


=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "C:/Xilinx/data/librtl.xst" Consulted

Optimizing unit <SPCLogic> ...

Mapping all equations...
Loading device for application Xst from file '2s200e.nph' in environment C:/Xilinx.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block SPCLogic, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200epq208-6 

 Number of Slices:                       3  out of   2352     0%  
 Number of 4 input LUTs:                 6  out of   4704     0%  
 Number of bonded IOBs:                 11  out of    146     7%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 9.359ns

=========================================================================

Completed process "Synthesize".



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Started process "Translate".


Command Line: ngdbuild -quiet -dd c:\xilinx\projects\spclogic/_ngo -i -p
xc2s200e-pq208-6 SPCLogic.ngc SPCLogic.ngd 

Reading NGO file "C:/Xilinx/projects/SPCLogic/SPCLogic.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "SPCLogic.ngd" ...

Writing NGDBUILD log file "SPCLogic.bld"...

NGDBUILD done.

Completed process "Translate".



Started process "Map".

Using target part "2s200epq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of 4 input LUTs:             6 out of  4,704    1%
Logic Distribution:
    Number of occupied Slices:                           3 out of  2,352    1%
    Number of Slices containing only related logic:      3 out of      3  100%
    Number of Slices containing unrelated logic:         0 out of      3    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:         6 out of  4,704    1%
   Number of bonded IOBs:            11 out of    142    7%

Total equivalent gate count for design:  36
Additional JTAG gate count for IOBs:  528
Peak Memory Usage:  55 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "SPCLogic_map.mrp" for details.

Completed process "Map".

Mapping Module SPCLogic . . .
MAP command line:
map -quiet -p xc2s200e-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o SPCLogic_map.ncd SPCLogic.ngd SPCLogic.pcf
Mapping Module SPCLogic: DONE



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Started process "Create Schematic Symbol".

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    SPCLogic.v
No errors or warnings

JHDPARSE complete -    0 errors,    0 warnings.


Release 5.2.03i - spl2sym F.31
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Completed process "Create Schematic Symbol".



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