# Verilog : PDCL (jhdparse)
__projnav/SPCLogic_jhdparse_tcl.rsp
# Verilog : PDCL (jhdparse)
__projnav/SPCLogic_jhdparse_tcl.rsp
# xst flow : RunXST
SPCLogic.syr
SPCLogic.ngr
SPCLogic.prj
SPCLogic.sprj
SPCLogic.ana
SPCLogic.stx
SPCLogic.cmd_log
# Verilog : PDCL (jhdparse)
__projnav/SPCLogic_jhdparse_tcl.rsp
# xst flow : RunXST
SPCLogic.syr
SPCLogic.ngr
SPCLogic.prj
SPCLogic.sprj
SPCLogic.ana
SPCLogic.stx
SPCLogic.cmd_log
# Verilog : PDCL (jhdparse)
__projnav/SPCLogic_jhdparse_tcl.rsp
# Verilog : PDCL (jhdparse)
__projnav/SPCLogic_jhdparse_tcl.rsp
# xst flow : RunXST
SPCLogic.syr
SPCLogic.ngr
SPCLogic.prj
SPCLogic.sprj
SPCLogic.ana
SPCLogic.stx
SPCLogic.cmd_log
# Verilog : PDCL (jhdparse)
__projnav/SPCLogic_jhdparse_tcl.rsp
# xst flow : RunXST
SPCLogic.syr
SPCLogic.ngr
SPCLogic.prj
SPCLogic.sprj
SPCLogic.ana
SPCLogic.stx
SPCLogic.cmd_log
# Verilog : PDCL (jhdparse)
__projnav/SPCLogic_jhdparse_tcl.rsp
# xst flow : RunXST
SPCLogic.syr
SPCLogic.ngr
SPCLogic.prj
SPCLogic.sprj
SPCLogic.ana
SPCLogic.stx
SPCLogic.cmd_log
# Verilog : PDCL (jhdparse)
__projnav/SPCLogic_jhdparse_tcl.rsp
# Verilog : PDCL (jhdparse)
__projnav/SPCLogic_jhdparse_tcl.rsp
# xst flow : RunXST
SPCLogic.syr
SPCLogic.ngr
SPCLogic.prj
SPCLogic.sprj
SPCLogic.ana
SPCLogic.stx
SPCLogic.cmd_log
# Verilog : PDCL (jhdparse)
__projnav/SPCLogic_jhdparse_tcl.rsp
# Verilog : PDCL (jhdparse)
__projnav/SPCLogic_jhdparse_tcl.rsp
# Verilog : Create Schematic Symbol
__projnav/jhdparse.log
# xst flow : RunXST
SPCLogic.syr
SPCLogic.ngr
SPCLogic.prj
SPCLogic.sprj
SPCLogic.ana
SPCLogic.stx
SPCLogic.cmd_log
# Verilog : PDCL (jhdparse)
__projnav/SPCLogic_jhdparse_tcl.rsp
# xst flow : RunXST
SPCLogic.syr
SPCLogic.ngr
SPCLogic.prj
SPCLogic.sprj
SPCLogic.ana
SPCLogic.stx
SPCLogic.cmd_log
SPCLogic.ngc
# Verilog : PDCL (jhdparse)
__projnav/SPCLogic_jhdparse_tcl.rsp
# Verilog : PDCL (jhdparse)
__projnav/SPCLogic_jhdparse_tcl.rsp
# xst flow : RunXST
SPCLogic.syr
SPCLogic.ngr
SPCLogic.prj
SPCLogic.sprj
SPCLogic.ana
SPCLogic.stx
SPCLogic.cmd_log
SPCLogic.ngc
# Verilog : PDCL (jhdparse)
__projnav/SPCLogic_jhdparse_tcl.rsp
# xst flow : RunXST
SPCLogic.syr
SPCLogic.ngr
SPCLogic.prj
SPCLogic.sprj
SPCLogic.ana
SPCLogic.stx
SPCLogic.cmd_log
SPCLogic.ngc
# Verilog : PDCL (jhdparse)
__projnav/SPCLogic_jhdparse_tcl.rsp
# Verilog : PDCL (jhdparse)
__projnav/SPCLogic_jhdparse_tcl.rsp
# Verilog : PDCL (jhdparse)
__projnav/SPCLogic_jhdparse_tcl.rsp
# Verilog : PDCL (jhdparse)
__projnav/SPCLogic_jhdparse_tcl.rsp
# Verilog : PDCL (jhdparse)
__projnav/SPCLogic_jhdparse_tcl.rsp
# Verilog : Create Schematic Symbol
__projnav/jhdparse.log
# xst flow : RunXST
SPCLogic.syr
SPCLogic.ngr
SPCLogic.prj
SPCLogic.sprj
SPCLogic.ana
SPCLogic.stx
SPCLogic.cmd_log
SPCLogic.ngc
# Verilog : PDCL (jhdparse)
__projnav/SPCLogic_jhdparse_tcl.rsp
# Verilog : Create Schematic Symbol
__projnav/jhdparse.log
# xst flow : RunXST
SPCLogic.syr
SPCLogic.ngr
SPCLogic.prj
SPCLogic.sprj
SPCLogic.ana
SPCLogic.stx
SPCLogic.cmd_log
SPCLogic.ngc
# Verilog : PDCL (jhdparse)
__projnav/SPCLogic_jhdparse_tcl.rsp
# Verilog : Create Schematic Symbol
__projnav/jhdparse.log
# xst flow : RunXST
SPCLogic.syr
SPCLogic.ngr
SPCLogic.prj
SPCLogic.sprj
SPCLogic.ana
SPCLogic.stx
SPCLogic.cmd_log
SPCLogic.ngc
# Verilog : PDCL (jhdparse)
__projnav/SPCLogic_jhdparse_tcl.rsp
# Verilog : PDCL (jhdparse)
__projnav/SPCLogic_jhdparse_tcl.rsp
# Verilog : PDCL (jhdparse)
__projnav/SPCLogic_jhdparse_tcl.rsp
# xst flow : RunXST
SPCLogic.syr
SPCLogic.ngr
SPCLogic.prj
SPCLogic.sprj
SPCLogic.ana
SPCLogic.stx
SPCLogic.cmd_log
SPCLogic.ngc
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
c:\xilinx\projects\spclogic/_ngo
SPCLogic.ngd
SPCLogic_ngdbuild.nav
SPCLogic.bld
.untf
SPCLogic.cmd_log
# Implementation : Map
SPCLogic.nc1
SPCLogic.mrp
SPCLogic.pcf
SPCLogic.ngm
SPCLogic_map.ngm
SPCLogic.mdf
SPCLogic_map.ncd
__projnav/map.log
SPCLogic.cmd_log
# ProjNav -> New Source -> TBW
__projnav\hb_cmds
# ModelSim : Simulate Behavioral Verilog Model
__projnav/SPCLogic_tb_createfdo.rsp
SPCLogic_tb.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Verilog : PDCL (jhdparse)
__projnav/SPCLogic_jhdparse_tcl.rsp
# Verilog : PDCL (jhdparse)
__projnav/SPCLogic_jhdparse_tcl.rsp
# xst flow : RunXST
SPCLogic.syr
SPCLogic.ngr
SPCLogic.prj
SPCLogic.sprj
SPCLogic.ana
SPCLogic.stx
SPCLogic.cmd_log
SPCLogic.ngc
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
c:\xilinx\projects\spclogic/_ngo
SPCLogic.ngd
SPCLogic_ngdbuild.nav
SPCLogic.bld
.untf
SPCLogic.cmd_log
# Implementation : Map
SPCLogic.nc1
SPCLogic.mrp
SPCLogic.pcf
SPCLogic.ngm
SPCLogic_map.ngm
SPCLogic.mdf
SPCLogic_map.ncd
__projnav/map.log
SPCLogic.cmd_log
# Verilog : Create Schematic Symbol
__projnav/jhdparse.log
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
SPCLogic_tb.vhw
SPCLogic_tb.ano
SPCLogic_tb.tfw
# ModelSim : Simulate Behavioral Verilog Model
__projnav/SPCLogic_tb_createfdo.rsp
SPCLogic_tb.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
