JDF F
// Created by Project Navigator ver 1.0
PROJECT RegTest
DESIGN regtest Normal
DEVFAM spartan2e
DEVFAMTIME 0
DEVICE xc2s200e
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
FLOW XST Verilog
FLOWTIME 0
MODULE RegTest_sch.sch
MODSTYLE regtest_sch Normal
MODULE RegNonM.v
MODSTYLE RegFile Normal
[STRATEGY-LIST]
Normal=True
