//Filename = RegFile.v
//Written by Stephen Schnelle
//This is a simple program that constructs a register file and allows data to be output from a given register or data to be inserted into a selected register

module RegFile(RegSelect1, RegSelect2, RegDataWrite, RegWrite, RegDataOut1, RegDataOut2, CLK);
input RegWrite,CLK;
input [3:0] RegSelect1, RegSelect2;
input [15:0] RegDataWrite;

output [15:0] RegDataOut1, RegDataOut2;

reg [15:0] RegDataOut1,RegDataOut2,Reg0,Reg1,Reg2,Reg3,Reg4,Reg5,Reg6,Reg7,Reg8,Reg9,Reg10,Reg11,Reg12,Reg13,Reg14,Reg15;		//Removed RegDataWrite
//reg [3:0] RegSelect1, RegSelect2;

always @ (posedge CLK)				//implements sequential logic using positive edge of clock
begin

case (RegSelect1)									//use case statement to choose register(s) that get read and which one gets written to
0:		begin RegDataOut1<=Reg0; end
1:		begin RegDataOut1<=Reg1; end
2:		begin RegDataOut1<=Reg2; end
3:		begin RegDataOut1<=Reg3; end
4:		begin RegDataOut1<=Reg4; end
5:		begin RegDataOut1<=Reg5; end
6:		begin RegDataOut1<=Reg6; end
7:		begin RegDataOut1<=Reg7; end
8:		begin RegDataOut1<=Reg8; end
9:		begin RegDataOut1<=Reg9; end
10:		begin RegDataOut1<=Reg10; end
11:		begin RegDataOut1<=Reg11; end
12:		begin RegDataOut1<=Reg12; end
13:		begin RegDataOut1<=Reg13; end
14:		begin RegDataOut1<=Reg14; end
15:		begin RegDataOut1<=Reg15; end

default: 	begin RegDataOut1<=Reg0; end
endcase

case (RegSelect2)
0:		begin RegDataOut2<=Reg0; end
1:		begin RegDataOut2<=Reg1; end
2:		begin RegDataOut2<=Reg2; end
3:		begin RegDataOut2<=Reg3; end
4:		begin RegDataOut2<=Reg4; end
5:		begin RegDataOut2<=Reg5; end
6:		begin RegDataOut2<=Reg6; end
7:		begin RegDataOut2<=Reg7; end
8:		begin RegDataOut2<=Reg8; end
9:		begin RegDataOut2<=Reg9; end
10:		begin RegDataOut2<=Reg10; end
11:		begin RegDataOut2<=Reg11; end
12:		begin RegDataOut2<=Reg12; end
13:		begin RegDataOut2<=Reg13; end
14:		begin RegDataOut2<=Reg14; end
15:		begin RegDataOut2<=Reg15; end

default: 	begin RegDataOut2<=Reg0; end
endcase


if (RegWrite==1)						//checks control signal for write each clock cycle
begin
case (RegSelect1)
0:		begin Reg0<=RegDataWrite; end
1:		begin Reg1<=RegDataWrite; end
2:		begin Reg2<=RegDataWrite; end
3:		begin Reg3<=RegDataWrite; end
4:		begin Reg4<=RegDataWrite; end
5:		begin Reg5<=RegDataWrite; end
6:		begin Reg6<=RegDataWrite; end
7:		begin Reg7<=RegDataWrite; end
8:		begin Reg8<=RegDataWrite; end
9:		begin Reg9<=RegDataWrite; end
10:		begin Reg10<=RegDataWrite; end
11:		begin Reg11<=RegDataWrite; end
12:		begin Reg12<=RegDataWrite; end
13:		begin Reg13<=RegDataWrite; end
14:		begin Reg14<=RegDataWrite; end
15:		begin Reg15<=RegDataWrite; end

default: 	begin RegDataOut2<=Reg0; end
endcase
end

end

endmodule