library verilog;
use verilog.vl_types.all;
entity regfile is
    port(
        regselect1      : in     vl_logic_vector(3 downto 0);
        regselect2      : in     vl_logic_vector(3 downto 0);
        regdatawrite    : in     vl_logic_vector(15 downto 0);
        regwrite        : in     vl_logic;
        regdataout1     : out    vl_logic_vector(15 downto 0);
        regdataout2     : out    vl_logic_vector(15 downto 0);
        clock           : in     vl_logic
    );
end regfile;
