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JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    C:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning    CustomRegFile.v
Writing CustomRegFile.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



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Started process "Create Schematic Symbol".

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    CustomRegFile.v
     Parameter 'NUM_REGS' with value '16'
.No errors or warnings

JHDPARSE complete -    0 errors,    0 warnings.


Release 5.2.03i - spl2sym F.31
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Completed process "Create Schematic Symbol".



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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "RegFile.prj"
Compiling include file "CustomRegFile.v"
Module <RegFile> compiled
Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"
No errors in compilation

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analysis of file <RegFile.prj> succeeded.
 
 
Analyzing top module <RegFile>.
Module <RegFile> is correct for synthesis.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <RegFile>.
    Related source file is CustomRegFile.v.
INFO:Xst:1435 - Unable to extract a block RAM for signal <Reg>. The read/write synchronization appears to be READ_FIRST and is not available for the selected family. A distributed RAM will usually be created instead. To take advantage of block RAM resources, you may want to revisit your RAM synchronization or check check available device families.
INFO:Xst:1435 - Unable to extract a block RAM for signal <Reg>. The read/write synchronization appears to be READ_FIRST and is not available for the selected family. A distributed RAM will usually be created instead. To take advantage of block RAM resources, you may want to revisit your RAM synchronization or check check available device families.
    Found 16x16-bit dual-port distributed RAM for signal <Reg>.
    -----------------------------------------------------------------------
    | aspect ratio       | 16-word x 16-bit                    |          |
    | clock              | connected to signal <CLK>           | rise     |
    | write enable       | connected to signal <RegWrite>      | high     |
    | address            | connected to signal <RegSelect1>    |          |
    | dual address       | connected to signal <RegSelect2>    |          |
    | data in            | connected to signal <RegDataWrite>  |          |
    | data out           | connected to internal node          |          |
    | dual data out      | connected to internal node          |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 16-bit register for signal <RegDataOut1>.
    Found 16-bit register for signal <RegDataOut2>.
    Summary:
	inferred   1 RAM(s).
	inferred  32 D-type flip-flop(s).
Unit <RegFile> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# RAMs                             : 1
  16x16-bit dual-port distributed RAM: 1
# Registers                        : 2
  16-bit register                  : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "C:/Xilinx/data/librtl.xst" Consulted

Optimizing unit <RegFile> ...

Mapping all equations...
Loading device for application Xst from file '2s200e.nph' in environment C:/Xilinx.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block RegFile, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200epq208-6 

 Number of Slices:                      33  out of   2352     1%  
 Number of Slice Flip Flops:            32  out of   4704     0%  
 Number of 4 input LUTs:                16  out of   4704     0%  
 Number of bonded IOBs:                 57  out of    146    39%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 48    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 3.212ns (Maximum Frequency: 311.333MHz)
   Minimum input arrival time before clock: 5.616ns
   Maximum output required time after clock: 6.514ns
   Maximum combinational path delay: No path found

=========================================================================

Completed process "Synthesize".



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Started process "Translate".


Command Line: ngdbuild -quiet -dd
c:\xilinx\projects\merkleregfile\regfile\customregfile/_ngo -i -p
xc2s200e-pq208-6 RegFile.ngc RegFile.ngd 

Reading NGO file
"C:/Xilinx/projects/MerkleRegFile/RegFile/CustomRegFile/RegFile.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "RegFile.ngd" ...

Writing NGDBUILD log file "RegFile.bld"...

NGDBUILD done.

Completed process "Translate".



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Started process "Map".

Using target part "2s200epq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
Logic Distribution:
    Number of occupied Slices:                          16 out of  2,352    1%
    Number of Slices containing only related logic:     16 out of     16  100%
    Number of Slices containing unrelated logic:         0 out of     16    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:           32 out of  4,704    1%
      Number used for Dual Port RAMs:              32
      (Two LUTs used per Dual Port RAM)
   Number of bonded IOBs:            57 out of    142   40%
      IOB Flip Flops:                              32
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  2,304
Additional JTAG gate count for IOBs:  2,784
Peak Memory Usage:  56 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "RegFile_map.mrp" for details.

Completed process "Map".

Mapping Module RegFile . . .
MAP command line:
map -quiet -p xc2s200e-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o RegFile_map.ncd RegFile.ngd RegFile.pcf
Mapping Module RegFile: DONE


