/*********************************************************/
// MODULE:			RegFile
//
// FILE NAME:			RegFile.v
// VERSION:			1.0
// DATE:			Oct 29, 2003
// AUTHOR:			Stephen Schnelle with much help from Dr. Merkle
//
// DESCRIPTION:	This module defines a register file with 
//                sixteen 16-bit registers, two read ports, 
//                and one write port.  
//
/*********************************************************/
module RegFile(
   RegSelect1,
   RegSelect2,
   //WriteReg,
   RegDataWrite,
   RegWrite,
   RegDataOut1,               
   RegDataOut2,
   CLK);

// Definitions

parameter NUM_REGS = 16;
`define ADDR_SZ 4
`define REG_WIDTH 16

// Inputs

input [`ADDR_SZ-1:0] RegSelect1;
input [`ADDR_SZ-1:0] RegSelect2;
//input [`ADDR_SZ-1:0] WriteReg;
input [`REG_WIDTH-1:0] RegDataWrite;
input RegWrite;
input CLK;

// Outputs

output [`REG_WIDTH-1:0] RegDataOut1;
output [`REG_WIDTH-1:0] RegDataOut2;

// Signals

reg [`REG_WIDTH-1:0] RegDataOut1;
reg [`REG_WIDTH-1:0] RegDataOut2;

// The registers

reg [`REG_WIDTH-1:0] Reg [NUM_REGS-1:0];

// Operation

always @ ( posedge CLK ) begin
   RegDataOut1 <= Reg[ RegSelect1 ];
   RegDataOut2 <= Reg[ RegSelect2 ];
   if ( RegWrite )
      Reg[ RegSelect1 ] <= RegDataWrite;
end

endmodule
