Release 5.2.03i - xst F.31
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
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--> Reading design: RegFile.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Low Level Synthesis
  6) Final Report
     6.1) Device utilization summary
     6.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : RegFile.prj
Input Format                       : VERILOG
Ignore Synthesis Constraint File   : NO
Verilog Search Path                : 
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : RegFile
Output Format                      : NGC
Target Device                      : xc2s200e-6pq208

---- Source Options
Top Module Name                    : RegFile
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Top module area constraint         : 100
Top module allowed area overflow   : 5

---- Other Options
read_cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "RegFile.prj"
Compiling include file "CustomRegFile.v"
Module <RegFile> compiled
Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"
No errors in compilation

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analysis of file <RegFile.prj> succeeded.
 
 
Analyzing top module <RegFile>.
Module <RegFile> is correct for synthesis.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <RegFile>.
    Related source file is CustomRegFile.v.
INFO:Xst:1435 - Unable to extract a block RAM for signal <Reg>. The read/write synchronization appears to be READ_FIRST and is not available for the selected family. A distributed RAM will usually be created instead. To take advantage of block RAM resources, you may want to revisit your RAM synchronization or check check available device families.
INFO:Xst:1435 - Unable to extract a block RAM for signal <Reg>. The read/write synchronization appears to be READ_FIRST and is not available for the selected family. A distributed RAM will usually be created instead. To take advantage of block RAM resources, you may want to revisit your RAM synchronization or check check available device families.
    Found 16x16-bit dual-port distributed RAM for signal <Reg>.
    -----------------------------------------------------------------------
    | aspect ratio       | 16-word x 16-bit                    |          |
    | clock              | connected to signal <CLK>           | rise     |
    | write enable       | connected to signal <RegWrite>      | high     |
    | address            | connected to signal <RegSelect1>    |          |
    | dual address       | connected to signal <RegSelect2>    |          |
    | data in            | connected to signal <RegDataWrite>  |          |
    | data out           | connected to internal node          |          |
    | dual data out      | connected to internal node          |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 16-bit register for signal <RegDataOut1>.
    Found 16-bit register for signal <RegDataOut2>.
    Summary:
	inferred   1 RAM(s).
	inferred  32 D-type flip-flop(s).
Unit <RegFile> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# RAMs                             : 1
  16x16-bit dual-port distributed RAM: 1
# Registers                        : 2
  16-bit register                  : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "C:/Xilinx/data/librtl.xst" Consulted

Optimizing unit <RegFile> ...

Mapping all equations...
Loading device for application Xst from file '2s200e.nph' in environment C:/Xilinx.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block RegFile, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : RegFile.ngr
Top Level Output File Name         : RegFile
Output Format                      : NGC
Optimization Criterion             : Speed
Keep Hierarchy                     : NO
Macro Generator                    : macro+

Design Statistics
# IOs                              : 58

Macro Statistics :
# RAM                              : 1
#      16x16-bit dual-port distributed RAM: 1
# Registers                        : 2
#      16-bit register             : 2

Cell Usage :
# FlipFlops/Latches                : 32
#      FD                          : 32
# RAMS                             : 16
#      RAM16X1D                    : 16
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 57
#      IBUF                        : 25
#      OBUF                        : 32
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200epq208-6 

 Number of Slices:                      33  out of   2352     1%  
 Number of Slice Flip Flops:            32  out of   4704     0%  
 Number of 4 input LUTs:                16  out of   4704     0%  
 Number of bonded IOBs:                 57  out of    146    39%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 48    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 3.212ns (Maximum Frequency: 311.333MHz)
   Minimum input arrival time before clock: 5.616ns
   Maximum output required time after clock: 6.514ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'CLK'
Delay:               3.212ns (Levels of Logic = 0)
  Source:            Mram_Reg_inst_ramx_6
  Destination:       RegDataOut2_6
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: Mram_Reg_inst_ramx_6 to RegDataOut2_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     RAM16X1D:WCLK->DPO    1   1.568   0.920  Mram_Reg_inst_ramx_6 (_n0001<6>)
     FD:D                      0.724          RegDataOut2_6
    ----------------------------------------
    Total                      3.212ns (2.292ns logic, 0.920ns route)
                                       (71.4% logic, 28.6% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
Offset:              5.616ns (Levels of Logic = 2)
  Source:            RegSelect1<0>
  Destination:       RegDataOut2_6
  Destination Clock: CLK rising

  Data Path: RegSelect1<0> to RegDataOut2_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            16   0.797   2.240  RegSelect1_0_IBUF (RegSelect1_0_IBUF)
     RAM16X1D:A0->DPO      1   0.935   0.920  Mram_Reg_inst_ramx_6 (_n0001<6>)
     FD:D                      0.724          RegDataOut2_6
    ----------------------------------------
    Total                      5.616ns (2.456ns logic, 3.160ns route)
                                       (43.7% logic, 56.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
Offset:              6.514ns (Levels of Logic = 1)
  Source:            RegDataOut2_4
  Destination:       RegDataOut2<4>
  Source Clock:      CLK rising

  Data Path: RegDataOut2_4 to RegDataOut2<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               1   0.992   0.920  RegDataOut2_4 (RegDataOut2_4)
     OBUF:I->O                 4.602          RegDataOut2_4_OBUF (RegDataOut2<4>)
    ----------------------------------------
    Total                      6.514ns (5.594ns logic, 0.920ns route)
                                       (85.9% logic, 14.1% route)

=========================================================================
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