Release 5.2.03i - xst F.31
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
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CPU : 0.00 / 0.30 s | Elapsed : 0.00 / 0.00 s
 
--> Reading design: barrel_shifter.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Low Level Synthesis
  6) Final Report
     6.1) Device utilization summary
     6.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : barrel_shifter.prj
Input Format                       : VERILOG
Ignore Synthesis Constraint File   : NO
Verilog Search Path                : 
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : barrel_shifter
Output Format                      : NGC
Target Device                      : xc2s200e-6pq208

---- Source Options
Top Module Name                    : barrel_shifter
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Top module area constraint         : 100
Top module allowed area overflow   : 5

---- Other Options
read_cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "barrel_shifter.prj"
Compiling include file "BarrelSh.v"
Module <barrel_shifter> compiled
Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"
No errors in compilation

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analysis of file <barrel_shifter.prj> succeeded.
 
 
Analyzing top module <barrel_shifter>.
Module <barrel_shifter> is correct for synthesis.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <barrel_shifter>.
    Related source file is BarrelSh.v.
    Found 16-bit shifter logical left for signal <DataOut>.
    Summary:
	inferred   1 Combinational logic shifter(s).
Unit <barrel_shifter> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Logic shifters                   : 1
  16-bit shifter logical left      : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "C:/Xilinx/data/librtl.xst" Consulted

Optimizing unit <barrel_shifter> ...

Mapping all equations...
Loading device for application Xst from file '2s200e.nph' in environment C:/Xilinx.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block barrel_shifter, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : barrel_shifter.ngr
Top Level Output File Name         : barrel_shifter
Output Format                      : NGC
Optimization Criterion             : Speed
Keep Hierarchy                     : NO
Macro Generator                    : macro+

Design Statistics
# IOs                              : 36

Macro Statistics :
# Logic shifters                   : 1
#      16-bit shifter logical left : 1

Cell Usage :
# BELS                             : 64
#      LUT2                        : 2
#      LUT3                        : 33
#      LUT4                        : 21
#      MUXF5                       : 8
# IO Buffers                       : 36
#      IBUF                        : 20
#      OBUF                        : 16
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200epq208-6 

 Number of Slices:                      31  out of   2352     1%  
 Number of 4 input LUTs:                56  out of   4704     1%  
 Number of bonded IOBs:                 36  out of    146    24%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 14.095ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               14.095ns (Levels of Logic = 6)
  Source:            ShiftDistance<1>
  Destination:       DataOut<15>

  Data Path: ShiftDistance<1> to DataOut<15>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            19   0.797   2.480  ShiftDistance_1_IBUF (ShiftDistance_1_IBUF)
     LUT3:I1->O            4   0.468   1.280  SF1201 (SF120)
     LUT3:I0->O            2   0.468   1.072  SF1281 (SF128)
     LUT3:I0->O            2   0.468   1.072  SF1441 (SF144)
     LUT3:I1->O            1   0.468   0.920  Mshift_DataOut_Result<15>65 (DataOut_15_OBUF)
     OBUF:I->O                 4.602          DataOut_15_OBUF (DataOut<15>)
    ----------------------------------------
    Total                     14.095ns (7.271ns logic, 6.824ns route)
                                       (51.6% logic, 48.4% route)

=========================================================================
CPU : 2.64 / 3.13 s | Elapsed : 2.00 / 3.00 s
 
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Total memory usage is 66296 kilobytes


