Release 5.2.03i - Map F.31
Xilinx Mapping Report File for Design 'barrel_shifter'

Design Information
------------------
Command Line   : C:/Xilinx/bin/nt/map.exe -quiet -p xc2s200e-pq208-6 -cm area
-pr b -k 4 -c 100 -tx off -o barrel_shifter_map.ncd barrel_shifter.ngd
barrel_shifter.pcf 
Target Device  : x2s200e
Target Package : pq208
Target Speed   : -6
Mapper Version : spartan2e -- $Revision: 1.4 $
Mapped Date    : Thu Oct 30 08:51:52 2003

Design Summary
--------------
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of 4 input LUTs:            56 out of  4,704    1%
Logic Distribution:
    Number of occupied Slices:                          28 out of  2,352    1%
    Number of Slices containing only related logic:     28 out of     28  100%
    Number of Slices containing unrelated logic:         0 out of     28    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:        56 out of  4,704    1%
   Number of bonded IOBs:            36 out of    142   25%

Total equivalent gate count for design:  360
Additional JTAG gate count for IOBs:  1,728
Peak Memory Usage:  55 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------

Section 3 - Informational
-------------------------
INFO:LIT:95 - All of the external outputs in this design are using slew rate
   limited output drivers. The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the schematic.

Section 4 - Removed Logic Summary
---------------------------------

Section 5 - Removed Logic
-------------------------

Section 6 - IOB Properties
--------------------------

+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| DataIn<0>                          | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| DataIn<1>                          | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| DataIn<2>                          | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| DataIn<3>                          | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| DataIn<4>                          | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| DataIn<5>                          | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| DataIn<6>                          | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| DataIn<7>                          | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| DataIn<8>                          | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| DataIn<9>                          | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| DataIn<10>                         | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| DataIn<11>                         | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| DataIn<12>                         | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| DataIn<13>                         | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| DataIn<14>                         | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| DataIn<15>                         | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| DataOut<0>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| DataOut<1>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| DataOut<2>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| DataOut<3>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| DataOut<4>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| DataOut<5>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| DataOut<6>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| DataOut<7>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| DataOut<8>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| DataOut<9>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| DataOut<10>                        | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| DataOut<11>                        | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| DataOut<12>                        | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| DataOut<13>                        | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| DataOut<14>                        | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| DataOut<15>                        | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| ShiftDistance<0>                   | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| ShiftDistance<1>                   | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| ShiftDistance<2>                   | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| ShiftDistance<3>                   | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
+------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group Summary
------------------------------
No area groups were found in this design.

Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.
