# Verilog : PDCL (jhdparse)
__projnav/alu_jhdparse_tcl.rsp
# Bencher Waveform : PDCL (jhdparse)
# xst flow : RunXST
ALU.syr
ALU.ngr
ALU.prj
ALU.sprj
ALU.ana
ALU.stx
ALU.cmd_log
ALU.ngc
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
c:\has_to_be_here\alu/_ngo
ALU.ngd
ALU_ngdbuild.nav
ALU.bld
.untf
ALU.cmd_log
# Implementation : Map
ALU.nc1
ALU.mrp
ALU.pcf
ALU.ngm
ALU_map.ngm
ALU.mdf
ALU_map.ncd
__projnav/map.log
ALU.cmd_log
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
ALU.twr
ALU.twx
ALU.tsi
ALU.cmd_log
# Implmentation : Generate Post-Place & Route Static Timing
__projnav/nc1TOncd_tcl.rsp
ALU.ncd
ALU.par
ALU.pad
ALU.dly
ALU.xpi
ALU.grf
ALU.itr
ALU_last_par.ncd
__projnav/par.log
ALU.cmd_log
