Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    C:/Xilinx/yuy/verilog/src/iSE/unisim_comp.v
Scanning    alu.v
Writing alu.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "ALU.prj"
Compiling include file "alu.v"
Module <ALU> compiled
Compiling include file "C:/Xilinx/yuy/verilog/src/iSE/unisim_comp.v"
No errors in compilation

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analysis of file <ALU.prj> succeeded.
 
 
Analyzing top module <ALU>.
Module <ALU> is correct for synthesis.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <ALU>.
    Related source file is alu.v.
!!! ADJUST CONCAT SIZE AFTER UNARY MULT OPT !!!
!!! ADJUST CONCAT SIZE AFTER UNARY MULT OPT !!!
!!! ADJUST CONCAT SIZE AFTER UNARY MULT OPT !!!
!!! ADJUST CONCAT SIZE AFTER UNARY MULT OPT !!!
!!! ADJUST CONCAT SIZE AFTER UNARY MULT OPT !!!
    Found 15-bit adder carry out for signal <$n0012>.
    Found 16-bit adder carry out for signal <$n0013>.
    Found 17-bit subtractor for signal <F1>.
    Found 1-bit xor2 for signal <OV0>.
    Found 1-bit xor2 for signal <OV1>.
    Found 16-bit subtractor for signal <ralph1>.
    Summary:
	inferred   4 Adder/Subtracter(s).
Unit <ALU> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 4
  16-bit subtractor                : 1
  17-bit subtractor                : 1
  15-bit adder carry out           : 1
  16-bit adder carry out           : 1
# Xors                             : 2
  1-bit xor2                       : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "C:/Xilinx/yuy/data/librtl.xst" Consulted

Optimizing unit <ALU> ...

Mapping all equations...
Loading device for application Xst from file '2s200e.nph' in environment C:/Xilinx/yuy.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block ALU, actual ratio is 3.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200epq208-6 

 Number of Slices:                      62  out of   2352     2%  
 Number of 4 input LUTs:               117  out of   4704     2%  
 Number of bonded IOBs:                 52  out of    146    35%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 13.592ns

=========================================================================

Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -quiet -dd c:\has_to_be_here\alu/_ngo -i -p
xc2s200e-pq208-6 ALU.ngc ALU.ngd 

Reading NGO file "C:/has_to_be_here/ALU/ALU.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "ALU.ngd" ...

Writing NGDBUILD log file "ALU.bld"...

NGDBUILD done.

Completed process "Translate".



Started process "Map".

Using target part "2s200epq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of 4 input LUTs:           117 out of  4,704    2%
Logic Distribution:
    Number of occupied Slices:                          61 out of  2,352    2%
    Number of Slices containing only related logic:     61 out of     61  100%
    Number of Slices containing unrelated logic:         0 out of     61    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:       117 out of  4,704    2%
   Number of bonded IOBs:            52 out of    142   36%

Total equivalent gate count for design:  1,035
Additional JTAG gate count for IOBs:  2,496
Peak Memory Usage:  56 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "ALU_map.mrp" for details.

Completed process "Map".

Mapping Module ALU . . .
MAP command line:
map -quiet -p xc2s200e-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o ALU_map.ncd ALU.ngd ALU.pcf
Mapping Module ALU: DONE



Started process "Place & Route".

Release 5.2.03i - Par F.31
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.




Constraints file: ALU.pcf

Loading device database for application par from file "ALU_map.ncd".
   "ALU" is an NCD, version 2.37, device xc2s200e, package pq208, speed -6
Loading device for application par from file '2s200e.nph' in environment
C:/Xilinx/yuy.
Device speed data version:  PRODUCTION 1.17 2003-05-08.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs            52 out of 142    36%
      Number of LOCed External IOBs    0 out of 52      0%

   Number of SLICEs                   61 out of 2352    2%




Overall effort level (-ol):   2 (set by user)
Placer effort level (-pl):    2 (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    2 (set by user)


Phase 1.1
Phase 1.1 (Checksum:9897cf) REAL time: 6 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 6 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 6 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 6 secs 

Phase 5.8
..
Phase 5.8 (Checksum:9c3da7) REAL time: 6 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 6 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 6 secs 

Writing design to file ALU.ncd.

Total REAL time to placer completion: 6 secs 
Total CPU time to placer completion: 2 secs 


Starting Router          REAL time: 7 secs 

Phase 1: 400 unrouted;       REAL time: 7 secs 

Phase 2: 400 unrouted;       REAL time: 7 secs 

Phase 3: 98 unrouted;       REAL time: 7 secs 

Phase 4: 0 unrouted;       REAL time: 7 secs 

Finished Router          REAL time: 7 secs 

Total REAL time to router completion: 8 secs 
Total CPU time to router completion: 3 secs 

Generating "par" statistics.


All signals are completely routed.

Total REAL time to par completion: 8 secs 
Total CPU time to par completion: 4 secs 

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file ALU.ncd.


PAR done.

Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".


Loading device database for application trce.exe from file "ALU.ncd".
   "ALU" is an NCD, version 2.37, device xc2s200e, package pq208, speed -6
Loading device for application trce.exe from file '2s200e.nph' in environment
C:/Xilinx/yuy.

Analysis completed Mon Nov 03 23:07:09 2003
--------------------------------------------------------------------------------

Generating Report ...


Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module ALU . . .
PAR command line: par -w -ol 2 -t 1 ALU_map.ncd ALU.ncd ALU.pcf
PAR completed successfully


