# Xilinx CORE Generator 5.2.03i; Cores Update # 2
SELECT FD-based_Parallel_Register Spartan2 Xilinx,_Inc. 6.0
CSET data_width = 16
CSET async_init_value = 0
CSET set_clear_priority = clear_overrides_set
CSET ce_overrides = sync_controls_override_ce
CSET sync_init_value = 0
CSET clock_enable = true
CSET create_rpm = true
CSET asynchronous_settings = none
CSET synchronous_settings = none
CSET component_name = instructionreg
GENERATE
