Release 5.2.03i - xst F.31
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
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--> Reading design: ALU.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Low Level Synthesis
  6) Final Report
     6.1) Device utilization summary
     6.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : ALU.prj
Input Format                       : VERILOG
Ignore Synthesis Constraint File   : NO
Verilog Search Path                : 
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : ALU
Output Format                      : NGC
Target Device                      : xc2s200e-6fg456

---- Source Options
Top Module Name                    : ALU
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Top module area constraint         : 100
Top module allowed area overflow   : 5

---- Other Options
read_cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "ALU.prj"
Compiling include file "ALU.v"
Module <ALU> compiled
Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"
No errors in compilation

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analysis of file <ALU.prj> succeeded.
 
 
Analyzing top module <ALU>.
WARNING:Xst:905 - ALU.v line 11: The signals <operation, B, cin> are missing in the sensitivity list of always block.
WARNING:Xst:905 - ALU.v line 26: The signals <operation, A, cin> are missing in the sensitivity list of always block.
WARNING:Xst:905 - ALU.v line 41: The signals <operation, A, B> are missing in the sensitivity list of always block.
WARNING:Xst:905 - ALU.v line 56: The signals <A, B, cin> are missing in the sensitivity list of always block.
Module <ALU> is correct for synthesis.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <ALU>.
    Related source file is ALU.v.
WARNING:Xst:737 - Found 16-bit latch for signal <Result>.
    Found 16-bit 3-to-1 multiplexer for signal <$n0000>.
    Found 16-bit adder carry in for signal <$n0001>.
    Found 16-bit xor2 for signal <$n0002> created at line 17.
WARNING:Xst:647 - Input <bInvert<0>> is never used.
    Summary:
	inferred   1 Adder/Subtracter(s).
Unit <ALU> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Latches                          : 1
  16-bit latch                     : 1
# Multiplexers                     : 1
  16-bit 3-to-1 multiplexer        : 1
# Adders/Subtractors               : 1
  16-bit adder carry in            : 1
# Xors                             : 1
  16-bit xor2                      : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "C:/Xilinx/data/librtl.xst" Consulted

Optimizing unit <ALU> ...

Mapping all equations...
Loading device for application Xst from file '2s200e.nph' in environment C:/Xilinx.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block ALU, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : ALU.ngr
Top Level Output File Name         : ALU
Output Format                      : NGC
Optimization Criterion             : Speed
Keep Hierarchy                     : NO
Macro Generator                    : macro+

Design Statistics
# IOs                              : 52

Macro Statistics :
# Adders/Subtractors               : 1
#      16-bit adder carry in       : 1

Cell Usage :
# BELS                             : 80
#      LUT2                        : 17
#      LUT4                        : 32
#      MUXCY                       : 15
#      XORCY                       : 16
# FlipFlops/Latches                : 16
#      LD                          : 16
# IO Buffers                       : 51
#      IBUF                        : 35
#      OBUF                        : 16
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200efg456-6 

 Number of Slices:                      27  out of   2352     1%  
 Number of Slice Flip Flops:            16  out of   4704     0%  
 Number of 4 input LUTs:                49  out of   4704     1%  
 Number of bonded IOBs:                 51  out of    289    17%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
Result_15__n00011:O                | NONE(*)(Result_9_0)    | 16    |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: 6.457ns
   Maximum output required time after clock: 6.613ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'Result_15__n00011:O'
Offset:              6.457ns (Levels of Logic = 3)
  Source:            operation<0>
  Destination:       Result_9_0
  Destination Clock: Result_15__n00011:O falling

  Data Path: operation<0> to Result_9_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            33   0.797   3.080  operation_0_IBUF (operation_0_IBUF)
     LUT4:I2->O            1   0.468   0.920  Mmux__n0000_I6_Result45 (CHOICE567)
     LUT4:I3->O            1   0.468   0.000  Mmux__n0000_I6_Result47 (N5408)
     LD:D                      0.724          Result_9_0
    ----------------------------------------
    Total                      6.457ns (2.457ns logic, 4.000ns route)
                                       (38.1% logic, 61.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'Result_15__n00011:O'
Offset:              6.613ns (Levels of Logic = 1)
  Source:            Result_11_0
  Destination:       Result<11>
  Source Clock:      Result_15__n00011:O falling

  Data Path: Result_11_0 to Result<11>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   1.091   0.920  Result_11_0 (Result_11_0)
     OBUF:I->O                 4.602          Result_11_OBUF (Result<11>)
    ----------------------------------------
    Total                      6.613ns (5.693ns logic, 0.920ns route)
                                       (86.1% logic, 13.9% route)

=========================================================================
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Total memory usage is 68288 kilobytes


