[COREGEN.VHDL Component Instantiation.instructionreg]
type=template
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component instructionreg"
text005="    port ("
text006="    D: IN std_logic_VECTOR(15 downto 0);"
text007="    Q: OUT std_logic_VECTOR(15 downto 0);"
text008="    CLK: IN std_logic;"
text009="    CE: IN std_logic);"
text010="end component;"
text011=""
text012=""
text013=""
text014=""
text015=" "
text016="-------------------------------------------------------------"
text017=" "
text018="-- The following code must appear in the VHDL architecture body."
text019="-- Substitute your own instance name and net names."
text020=" "
text021="your_instance_name : instructionreg"
text022="        port map ("
text023="            D => D,"
text024="            Q => Q,"
text025="            CLK => CLK,"
text026="            CE => CE);"
text027=" "
[COREGEN.VERILOG Component Instantiation.instructionreg]
type=template
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="instructionreg YourInstanceName ("
text007="    .D(D),"
text008="    .Q(Q),"
text009="    .CLK(CLK),"
text010="    .CE(CE));"
text011=""
text012=" "
[COREGEN.VHDL Component Instantiation.datareg]
type=template
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component datareg"
text005="    port ("
text006="    D: IN std_logic_VECTOR(15 downto 0);"
text007="    Q: OUT std_logic_VECTOR(15 downto 0);"
text008="    CLK: IN std_logic);"
text009="end component;"
text010=""
text011=""
text012=""
text013=""
text014=" "
text015="-------------------------------------------------------------"
text016=" "
text017="-- The following code must appear in the VHDL architecture body."
text018="-- Substitute your own instance name and net names."
text019=" "
text020="your_instance_name : datareg"
text021="        port map ("
text022="            D => D,"
text023="            Q => Q,"
text024="            CLK => CLK);"
text025=" "
[COREGEN.VERILOG Component Instantiation.datareg]
type=template
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="datareg YourInstanceName ("
text007="    .D(D),"
text008="    .Q(Q),"
text009="    .CLK(CLK));"
text010=""
text011=" "
