//  C:\XILINX\BIN\CONTROL_DEVICE\CONTROL2.v
//  Verilog created by Xilinx's StateCAD 5.1i
//  Thu Nov 13 18:57:41 2003

//  This Verilog code (for use with Xilinx XST) was generated using: 
//  one-hot state assignment with boolean code format.
//  Minimization is enabled,  implied else is enabled, 
//  and outputs are speed optimized.

`timescale 1s/1s

module shell_control2(CLK,Op0,Op1,Op2,Op3,RESET,ALUop0,ALUop1,ALUSrcA,
	ALUSrcB0,ALUSrcB1,IorB,IorD,IRWrite,MemRead,MemtoReg,MemWrite,PCSource0,
	PCSource1,PCWrite,PCWriteCond,RegDst,RegWrite);

	input CLK;
	input Op0,Op1,Op2,Op3,RESET;
	output ALUop0,ALUop1,ALUSrcA,ALUSrcB0,ALUSrcB1,IorB,IorD,IRWrite,MemRead,
		MemtoReg,MemWrite,PCSource0,PCSource1,PCWrite,PCWriteCond,RegDst,RegWrite;

	reg [1:0] ALUop;
	reg [1:0] ALUSrcB;
	reg [1:0] PCSource;
	reg ALUop0,next_ALUop0,ALUop1,next_ALUop1,ALUSrcA,next_ALUSrcA,ALUSrcB0,
		next_ALUSrcB0,ALUSrcB1,next_ALUSrcB1,IorB,next_IorB,IorD,next_IorD,IRWrite,
		next_IRWrite,MemRead,next_MemRead,MemtoReg,next_MemtoReg,MemWrite,
		next_MemWrite,PCSource0,next_PCSource0,PCSource1,next_PCSource1,PCWrite,
		next_PCWrite,PCWriteCond,next_PCWriteCond,RegDst,next_RegDst,RegWrite,
		next_RegWrite;
	reg STATE0,next_STATE0,STATE1,next_STATE1,STATE2,next_STATE2,STATE3,
		next_STATE3,STATE4,next_STATE4,STATE5,next_STATE5,STATE6,next_STATE6,STATE7,
		next_STATE7,STATE8,next_STATE8,STATE9,next_STATE9,STATE10,next_STATE10,
		STATE11,next_STATE11,STATE12,next_STATE12;

	always @(posedge CLK or posedge RESET)
	begin
		if ( RESET ) begin
			STATE0 = 1;
			STATE1 = 0;
			STATE2 = 0;
			STATE3 = 0;
			STATE4 = 0;
			STATE5 = 0;
			STATE6 = 0;
			STATE7 = 0;
			STATE8 = 0;
			STATE9 = 0;
			STATE10 = 0;
			STATE11 = 0;
			STATE12 = 0;
			ALUSrcA = 0;
			IorB = 0;
			IorD = 0;
			MemtoReg = 0;
			MemWrite = 0;
			PCWriteCond = 0;
			RegDst = 0;
			RegWrite = 0;
			IRWrite = 1;
			MemRead = 1;
			PCWrite = 1;
			ALUop1 = 0;
			ALUop0 = 0;
			ALUSrcB1 = 0;
			ALUSrcB0 = 1;
			PCSource1 = 0;
			PCSource0 = 0;
		end else
		begin
			STATE0 = next_STATE0;
			STATE1 = next_STATE1;
			STATE2 = next_STATE2;
			STATE3 = next_STATE3;
			STATE4 = next_STATE4;
			STATE5 = next_STATE5;
			STATE6 = next_STATE6;
			STATE7 = next_STATE7;
			STATE8 = next_STATE8;
			STATE9 = next_STATE9;
			STATE10 = next_STATE10;
			STATE11 = next_STATE11;
			STATE12 = next_STATE12;
			ALUSrcA = next_ALUSrcA;
			IorB = next_IorB;
			IorD = next_IorD;
			IRWrite = next_IRWrite;
			MemRead = next_MemRead;
			MemtoReg = next_MemtoReg;
			MemWrite = next_MemWrite;
			PCWrite = next_PCWrite;
			PCWriteCond = next_PCWriteCond;
			RegDst = next_RegDst;
			RegWrite = next_RegWrite;
			ALUop1 = next_ALUop1;
			ALUop0 = next_ALUop0;
			ALUSrcB1 = next_ALUSrcB1;
			ALUSrcB0 = next_ALUSrcB0;
			PCSource1 = next_PCSource1;
			PCSource0 = next_PCSource0;
		end
	end

	always @ (Op0 or Op1 or Op2 or Op3 or STATE0 or STATE1 or STATE2 or STATE3 
		or STATE4 or STATE5 or STATE6 or STATE7 or STATE8 or STATE9 or STATE10 or 
		STATE11 or STATE12 or ALUop or ALUSrcB or PCSource)
	begin

		if ( STATE4 | STATE5 | STATE7 | STATE8 | STATE9 | STATE11 | STATE12 ) 
			next_STATE0=1;
		else next_STATE0=0;

		if ( STATE0 | Op1 & ~Op2 & ~Op3 & STATE1 | Op1 & Op3 & Op2 & STATE1 | Op1 &
			 Op0 & STATE1 ) next_STATE1=1;
		else next_STATE1=0;

		if ( Op0 & ~Op1 & Op2 & ~Op3 & STATE1 | ~Op0 & Op1 & Op2 & ~Op3 & STATE1 | 
			Op3 & STATE2 | ~Op2 & STATE2 | ~Op0 & ~Op1 & STATE2 | Op1 & Op0 & STATE2 ) 
			next_STATE2=1;
		else next_STATE2=0;

		if ( Op0 & ~Op1 & Op2 & ~Op3 & STATE2 ) next_STATE3=1;
		else next_STATE3=0;

		if ( STATE3 ) next_STATE4=1;
		else next_STATE4=0;

		if ( ~Op0 & Op1 & Op2 & ~Op3 & STATE2 ) next_STATE5=1;
		else next_STATE5=0;

		if ( ~Op1 & ~Op2 & Op3 & STATE1 | ~Op0 & ~Op2 & Op3 & STATE1 ) 
			next_STATE6=1;
		else next_STATE6=0;

		if ( STATE6 ) next_STATE7=1;
		else next_STATE7=0;

		if ( ~Op1 & Op2 & Op3 & STATE1 ) next_STATE8=1;
		else next_STATE8=0;

		if ( ~Op0 & ~Op1 & ~Op2 & ~Op3 & STATE1 ) next_STATE9=1;
		else next_STATE9=0;

		if ( ~Op0 & ~Op1 & Op2 & ~Op3 & STATE1 ) next_STATE10=1;
		else next_STATE10=0;

		if ( STATE10 ) next_STATE11=1;
		else next_STATE11=0;

		if ( Op0 & ~Op1 & ~Op2 & ~Op3 & STATE1 ) next_STATE12=1;
		else next_STATE12=0;


		ALUop= ( {2{STATE4}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{STATE5}}  & ( 2'h3 ) & 
			( 'h0 ) ) | ( {2{STATE7}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{STATE8}}  & ( 2'h3 )
			 & ( 'h0 ) ) | ( {2{STATE9}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{STATE11}}  & ( 
			2'h3 ) & ( 'h0 ) ) | ( {2{STATE12}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{STATE0}}  
			& ( 2'h3 ) & ( 'h0 ) ) | ( {2{STATE1}}  & ( {2{Op1}} & {2{Op0}} | {2{Op1}} & 
			{2{Op3}} & {2{Op2}} | {2{Op1}} & {2{~Op2}} & {2{~Op3}}  ) & ( 'h0 ) ) | ( {2{
			STATE1}}  & ( {2{~Op0}} & {2{~Op1}} & {2{~Op2}} & {2{~Op3}}  ) & ( 'h0 ) ) | 
			( {2{STATE1}}  & ( {2{~Op0}} & {2{~Op1}} & {2{Op2}} & {2{~Op3}}  ) & ( 'h0 ) 
			) | ( {2{STATE1}}  & ( {2{Op0}} & {2{~Op1}} & {2{~Op2}} & {2{~Op3}}  ) & ( 
			'h0 ) ) | ( {2{STATE1}}  & ( {2{Op0}} & {2{~Op1}} & {2{Op2}} & {2{~Op3}}  ) &
			 ( 'h0 ) ) | ( {2{STATE1}}  & ( {2{~Op0}} & {2{Op1}} & {2{Op2}} & {2{~Op3}}  
			) & ( 'h0 ) ) | ( {2{STATE2}}  & ( {2{Op1}} & {2{Op0}} | {2{~Op0}} & {2{~Op1
			}} | {2{~Op2}} | {2{Op3}}  ) & ( 'h0 ) ) | ( {2{STATE2}}  & ( {2{Op0}} & {2{~
			Op1}} & {2{Op2}} & {2{~Op3}}  ) & ( 'h0 ) ) | ( {2{STATE2}}  & ( {2{~Op0}} & 
			{2{Op1}} & {2{Op2}} & {2{~Op3}}  ) & ( 'h0 ) ) | ( {2{STATE3}}  & ( 2'h3 ) & 
			( 'h0 ) ) | ( {2{STATE1}}  & ( {2{~Op0}} & {2{~Op1}} & {2{~Op2}} & {2{Op3}}  
			) & ( 'h2 ) ) | ( {2{STATE1}}  & ( {2{Op0}} & {2{~Op1}} & {2{~Op2}} & {2{Op3
			}}  ) & ( 'h2 ) ) | ( {2{STATE1}}  & ( {2{~Op0}} & {2{Op1}} & {2{~Op2}} & {2{
			Op3}}  ) & ( 'h2 ) ) | ( {2{STATE6}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{STATE1}} 
			 & ( {2{~Op0}} & {2{~Op1}} & {2{Op2}} & {2{Op3}}  ) & ( 'h1 ) ) | ( {2{STATE1
			}}  & ( {2{Op0}} & {2{~Op1}} & {2{Op2}} & {2{Op3}}  ) & ( 'h1 ) ) | ( {2{
			STATE10}}  & ( 2'h3 ) & ( 'h0 ) );

		if ( Op3 & STATE2 | ~Op2 & STATE2 | ~Op0 & ~Op1 & STATE2 | Op1 & Op0 & 
			STATE2 | ~Op1 & ~Op2 & Op3 & STATE1 | ~Op0 & ~Op2 & Op3 & STATE1 | ~Op0 & 
			~Op1 & Op3 & STATE1 | Op0 & ~Op1 & Op2 & STATE1 | ~Op0 & Op2 & ~Op3 & STATE1 
			) next_ALUSrcA=1;
		else next_ALUSrcA=0;

		ALUSrcB= ( {2{STATE4}}  & ( 2'h3 ) & ( 'h1 ) ) | ( {2{STATE5}}  & ( 2'h3 ) 
			& ( 'h1 ) ) | ( {2{STATE7}}  & ( 2'h3 ) & ( 'h1 ) ) | ( {2{STATE8}}  & ( 2'h3
			 ) & ( 'h1 ) ) | ( {2{STATE9}}  & ( 2'h3 ) & ( 'h1 ) ) | ( {2{STATE11}}  & ( 
			2'h3 ) & ( 'h1 ) ) | ( {2{STATE12}}  & ( 2'h3 ) & ( 'h1 ) ) | ( {2{STATE0}}  
			& ( 2'h3 ) & ( 'h3 ) ) | ( {2{STATE1}}  & ( {2{Op1}} & {2{Op0}} | {2{Op1}} & 
			{2{Op3}} & {2{Op2}} | {2{Op1}} & {2{~Op2}} & {2{~Op3}}  ) & ( 'h3 ) ) | ( {2{
			STATE1}}  & ( {2{~Op0}} & {2{~Op1}} & {2{~Op2}} & {2{~Op3}}  ) & ( 'h0 ) ) | 
			( {2{STATE1}}  & ( {2{Op0}} & {2{~Op1}} & {2{~Op2}} & {2{~Op3}}  ) & ( 'h0 ) 
			) | ( {2{STATE1}}  & ( {2{Op0}} & {2{~Op1}} & {2{Op2}} & {2{~Op3}}  ) & ( 'h2
			 ) ) | ( {2{STATE1}}  & ( {2{~Op0}} & {2{Op1}} & {2{Op2}} & {2{~Op3}}  ) & ( 
			'h2 ) ) | ( {2{STATE2}}  & ( {2{Op1}} & {2{Op0}} | {2{~Op0}} & {2{~Op1}} | 
			{2{~Op2}} | {2{Op3}}  ) & ( 'h2 ) ) | ( {2{STATE2}}  & ( {2{Op0}} & {2{~Op1}}
			 & {2{Op2}} & {2{~Op3}}  ) & ( 'h0 ) ) | ( {2{STATE2}}  & ( {2{~Op0}} & {2{
			Op1}} & {2{Op2}} & {2{~Op3}}  ) & ( 'h0 ) ) | ( {2{STATE3}}  & ( 2'h3 ) & ( 
			'h0 ) ) | ( {2{STATE1}}  & ( {2{~Op0}} & {2{~Op1}} & {2{~Op2}} & {2{Op3}}  ) 
			& ( 'h0 ) ) | ( {2{STATE1}}  & ( {2{Op0}} & {2{~Op1}} & {2{~Op2}} & {2{Op3}} 
			 ) & ( 'h0 ) ) | ( {2{STATE1}}  & ( {2{~Op0}} & {2{Op1}} & {2{~Op2}} & {2{Op3
			}}  ) & ( 'h0 ) ) | ( {2{STATE6}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{STATE1}}  & 
			( {2{~Op0}} & {2{~Op1}} & {2{Op2}} & {2{Op3}}  ) & ( 'h0 ) ) | ( {2{STATE1}} 
			 & ( {2{Op0}} & {2{~Op1}} & {2{Op2}} & {2{Op3}}  ) & ( 'h0 ) ) | ( {2{STATE1
			}}  & ( {2{~Op0}} & {2{~Op1}} & {2{Op2}} & {2{~Op3}}  ) & ( 'h2 ) ) | ( {2{
			STATE10}}  & ( 2'h3 ) & ( 'h0 ) );

		if ( ~Op0 & ~Op1 & Op2 & ~Op3 & STATE1 ) next_IorB=1;
		else next_IorB=0;

		if ( Op0 & ~Op1 & Op2 & ~Op3 & STATE2 | ~Op0 & Op1 & Op2 & ~Op3 & STATE2 | 
			STATE10 ) next_IorD=1;
		else next_IorD=0;

		if ( STATE4 | STATE5 | STATE7 | STATE8 | STATE9 | STATE11 | STATE12 ) 
			next_IRWrite=1;
		else next_IRWrite=0;

		if ( STATE4 | STATE5 | STATE7 | STATE8 | STATE9 | STATE11 | STATE12 | Op0 &
			 ~Op1 & Op2 & ~Op3 & STATE2 | ~Op0 & Op1 & Op2 & ~Op3 & STATE2 ) 
			next_MemRead=1;
		else next_MemRead=0;

		if ( STATE3 | STATE10 ) next_MemtoReg=1;
		else next_MemtoReg=0;

		if ( ~Op0 & Op1 & Op2 & ~Op3 & STATE2 | STATE10 | Op0 & ~Op1 & ~Op2 & ~Op3 
			& STATE1 ) next_MemWrite=1;
		else next_MemWrite=0;

		PCSource= ( {2{STATE4}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{STATE5}}  & ( 2'h3 )
			 & ( 'h0 ) ) | ( {2{STATE7}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{STATE8}}  & ( 
			2'h3 ) & ( 'h0 ) ) | ( {2{STATE9}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{STATE11}}  
			& ( 2'h3 ) & ( 'h0 ) ) | ( {2{STATE12}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{STATE0
			}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{STATE1}}  & ( {2{Op1}} & {2{Op0}} | {2{Op1
			}} & {2{Op3}} & {2{Op2}} | {2{Op1}} & {2{~Op2}} & {2{~Op3}}  ) & ( 'h0 ) ) | 
			( {2{STATE1}}  & ( {2{Op0}} & {2{~Op1}} & {2{Op2}} & {2{~Op3}}  ) & ( 'h0 ) )
			 | ( {2{STATE1}}  & ( {2{~Op0}} & {2{~Op1}} & {2{Op2}} & {2{~Op3}}  ) & ( 'h0
			 ) ) | ( {2{STATE1}}  & ( {2{~Op0}} & {2{~Op1}} & {2{~Op2}} & {2{Op3}}  ) & (
			 'h0 ) ) | ( {2{STATE1}}  & ( {2{~Op0}} & {2{Op1}} & {2{Op2}} & {2{~Op3}}  ) 
			& ( 'h0 ) ) | ( {2{STATE1}}  & ( {2{Op0}} & {2{~Op1}} & {2{~Op2}} & {2{Op3}} 
			 ) & ( 'h0 ) ) | ( {2{STATE1}}  & ( {2{~Op0}} & {2{Op1}} & {2{~Op2}} & {2{Op3
			}}  ) & ( 'h0 ) ) | ( {2{STATE2}}  & ( {2{Op1}} & {2{Op0}} | {2{~Op0}} & {2{~
			Op1}} | {2{~Op2}} | {2{Op3}}  ) & ( 'h0 ) ) | ( {2{STATE2}}  & ( {2{Op0}} & 
			{2{~Op1}} & {2{Op2}} & {2{~Op3}}  ) & ( 'h0 ) ) | ( {2{STATE2}}  & ( {2{~Op0
			}} & {2{Op1}} & {2{Op2}} & {2{~Op3}}  ) & ( 'h0 ) ) | ( {2{STATE3}}  & ( 2'h3
			 ) & ( 'h0 ) ) | ( {2{STATE6}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{STATE1}}  & ( 
			{2{~Op0}} & {2{~Op1}} & {2{Op2}} & {2{Op3}}  ) & ( 'h1 ) ) | ( {2{STATE1}}  &
			 ( {2{Op0}} & {2{~Op1}} & {2{Op2}} & {2{Op3}}  ) & ( 'h1 ) ) | ( {2{STATE1}} 
			 & ( {2{~Op0}} & {2{~Op1}} & {2{~Op2}} & {2{~Op3}}  ) & ( 'h2 ) ) | ( {2{
			STATE10}}  & ( 2'h3 ) & ( 'h0 ) ) | ( {2{STATE1}}  & ( {2{Op0}} & {2{~Op1}} &
			 {2{~Op2}} & {2{~Op3}}  ) & ( 'h2 ) );

		if ( STATE4 | STATE5 | STATE7 | STATE8 | STATE9 | STATE11 | STATE12 | ~Op1 
			& ~Op2 & ~Op3 & STATE1 ) next_PCWrite=1;
		else next_PCWrite=0;

		if ( ~Op1 & Op2 & Op3 & STATE1 ) next_PCWriteCond=1;
		else next_PCWriteCond=0;

		if ( STATE6 ) next_RegDst=1;
		else next_RegDst=0;

		if ( STATE3 | STATE6 ) next_RegWrite=1;
		else next_RegWrite=0;

		next_ALUop1 = ALUop[1];
		next_ALUop0 = ALUop[0];
		next_ALUSrcB1 = ALUSrcB[1];
		next_ALUSrcB0 = ALUSrcB[0];
		next_PCSource1 = PCSource[1];
		next_PCSource0 = PCSource[0];
	end
endmodule

module control2(ALUop,ALUSrcB,Op,PCSource,CLK,RESET,ALUSrcA,IorB,IorD,IRWrite
	,MemRead,MemtoReg,MemWrite,PCWrite,PCWriteCond,RegDst,RegWrite);

	output [1:0] ALUop;
	output [1:0] ALUSrcB;
	input [3:0] Op;
	output [1:0] PCSource;
	input CLK;
	input RESET;
	output ALUSrcA,IorB,IorD,IRWrite,MemRead,MemtoReg,MemWrite,PCWrite,
		PCWriteCond,RegDst,RegWrite;

	wire [1:0] ALUop;
	wire [1:0] ALUSrcB;
	wire [3:0] Op;
	wire [1:0] PCSource;
	wire CLK;
	wire RESET;
	wire ALUSrcA,IorB,IorD,IRWrite,MemRead,MemtoReg,MemWrite,PCWrite,PCWriteCond
		,RegDst,RegWrite;

	shell_control2 part1(.CLK(CLK),.Op0(Op[0]),.Op1(Op[1]),.Op2(Op[2]),.Op3(
		Op[3]),.RESET(RESET),.ALUop0(ALUop[0]),.ALUop1(ALUop[1]),.ALUSrcA(ALUSrcA),
		.ALUSrcB0(ALUSrcB[0]),.ALUSrcB1(ALUSrcB[1]),.IorB(IorB),.IorD(IorD),.IRWrite(
		IRWrite),.MemRead(MemRead),.MemtoReg(MemtoReg),.MemWrite(MemWrite),.PCSource0
		(PCSource[0]),.PCSource1(PCSource[1]),.PCWrite(PCWrite),.PCWriteCond(
		PCWriteCond),.RegDst(RegDst),.RegWrite(RegWrite));


endmodule
