/*********************************************************/
// MODULE:			RegFile
//
// FILE NAME:		RegFile.v
// VERSION:			1.0
// DATE:				Feb 9, 2003
// AUTHOR:			Larry Merkle
//
// DESCRIPTION:	This module defines a register file with 
//                eight 16-bit registers, two read ports, 
//                and one write port.  
//
/*********************************************************/
module RegFile(
   ReadReg1,
   ReadReg2,
   WriteReg,
   WriteData,
   RegWrite,
   ReadData1,               
   ReadData2,
	Int1,
	Int2,
	ReadIntReg,
   CLK);

// Definitions

parameter NUM_REGS = 12;
`define ADDR_SZ 4
`define REG_WIDTH 16

// Inputs

input [`ADDR_SZ-1:0] ReadReg1;
input [`ADDR_SZ-1:0] ReadReg2;
input [`ADDR_SZ-1:0] WriteReg;
input [`REG_WIDTH-1:0] WriteData;
input [`REG_WIDTH-1:0] Int1;
input Int2;
input RegWrite;
input CLK;

// Outputs

output [`REG_WIDTH-1:0] ReadData1;
output [`REG_WIDTH-1:0] ReadData2;
output [`REG_WIDTH-1:0] ReadIntReg;

// Signals

reg [`REG_WIDTH-1:0] ReadData1;
reg [`REG_WIDTH-1:0] ReadData2;
reg [`REG_WIDTH-1:0] ReadIntReg;

// The registers

reg [`REG_WIDTH-1:0] Reg [NUM_REGS-1:0];

// Operation

always @ ( posedge CLK ) begin
   ReadData1 <= Reg[ ReadReg1 ];
   ReadData2 <= Reg[ ReadReg2 ];
	ReadIntReg <= Reg[ 11 ];
   if ( RegWrite )
      Reg[ WriteReg ] <= WriteData;
	if ( Int2 )
		Reg[ 11 ] <= Int1;
end

endmodule
