JDF F
// Created by Project Navigator ver 1.0
PROJECT ClassProject
DESIGN classproject Normal
DEVFAM spartan2e
DEVFAMTIME 0
DEVICE xc2s200e
DEVICETIME 0
DEVPKG fg456
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
FLOW XST Verilog
FLOWTIME 0
STIMULUS ALUTest.tbw Normal
STIMULUS regfile_tb.tbw Normal
DOCUMENT CONTROL2.DIA
MODULE datareg.xco
MODSTYLE datareg Normal
MODULE InstructionRegisterFile.sch
MODSTYLE instructionregisterfile Normal
MODULE ShiftLeft.v
MODSTYLE ShiftLeft Normal
MODULE CONTROL2.v
MODSTYLE shell_control2 Normal
MODSTYLE control2 Normal
MODULE x4to16ZeroExtend.v
MODSTYLE x4to16ZeroExtend Normal
MODULE x8to16ZeroExtend.v
MODSTYLE x8to16ZeroExtend Normal
MODULE instructionreg.xco
MODSTYLE instructionreg Normal
MODULE ALU.v
MODSTYLE ALU Normal
MODULE RegFile.v
MODSTYLE RegFile Normal
[STATUS-ALL]
ALU.ngcFile=WARNINGS,1068768062
ALU.v.jhdFile=WARNINGS,1068768062
RegFile.v.jhdFile=WARNINGS,1068768062
[STRATEGY-LIST]
Normal=True
