library verilog;
use verilog.vl_types.all;
entity \ALU\ is
    port(
        \A\             : in     vl_logic_vector(15 downto 0);
        \B\             : in     vl_logic_vector(15 downto 0);
        \bInvert\       : in     vl_logic_vector(0 downto 0);
        cin             : in     vl_logic_vector(0 downto 0);
        operation       : in     vl_logic_vector(1 downto 0);
        \Result\        : out    vl_logic_vector(15 downto 0)
    );
end \ALU\;
