Release 5.2.03i - xst F.31
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to .
CPU : 0.00 / 0.60 s | Elapsed : 0.00 / 1.00 s
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "x1bitalu.sprj"
Compiling include file "x1bitadder.vf"
Module <x1bitadder> compiled
Compiling include file "x1bitalu.vf"
Module <M2_1E_MXILINX_x1bitalu> compiled
Module <M8_1E_MXILINX_x1bitalu> compiled
Module <M2_1_MXILINX_x1bitalu> compiled
Module <x1bitalu> compiled
Compiling include file "C:/Xilinx/verilog/src/iSE/unisim_comp.v"
No errors in compilation
Analysis of file <x1bitalu.sprj> succeeded.

CPU : 1.28 / 1.88 s | Elapsed : 1.00 / 2.00 s
 
--> 

Total memory usage is 53376 kilobytes


