library verilog;
use verilog.vl_types.all;
entity x1bitalu is
    port(
        \Operation\     : in     vl_logic_vector(1 downto 0);
        a               : in     vl_logic;
        b               : in     vl_logic;
        ci              : in     vl_logic;
        less            : in     vl_logic;
        \Result\        : out    vl_logic;
        \aADDb\         : out    vl_logic;
        co              : out    vl_logic
    );
end x1bitalu;
