library verilog;
use verilog.vl_types.all;
entity overflow is
    port(
        \Result\        : in     vl_logic;
        a               : in     vl_logic;
        b               : in     vl_logic;
        binvert         : in     vl_logic;
        \Overflow\      : out    vl_logic
    );
end overflow;
