JDF F
// Created by Project Navigator ver 1.0
PROJECT ALU5bit
DESIGN alu16bit Normal
DEVFAM spartan2e
DEVFAMTIME 0
DEVICE xc2s200e
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -7
DEVSPEEDTIME 0
FLOW XST Verilog
FLOWTIME 0
STIMULUS x1bitaddertbw.tbw Normal
STIMULUS alu16bittbw.tbw Normal
STIMULUS overflowtbw.tbw Normal
STIMULUS x1bitalutbw.tbw Normal
MODULE x1bitALU.sch
MODSTYLE x1bitalu Normal
MODULE overflow.sch
MODSTYLE overflow Normal
MODULE ALU16bit.sch
MODSTYLE alu16bit Normal
MODULE x1bitadder.sch
MODSTYLE x1bitadder Normal
MODULE zero.sch
MODSTYLE zero Normal
[STRATEGY-LIST]
Normal=True
