// Verilog model created from schematic x1bitadder.sch - Tue Oct 14 15:44:42 2003


`timescale 1ns / 1ps

module x1bitadder(a, b, ci, co, do);

 input a;
 input b;
 input ci;
output co;
output do;

wire ab;
wire aci;
wire bci;

AND2 XLXI_1 (.I0(b), .I1(a), .O(ab));
AND2 XLXI_2 (.I0(ci), .I1(a), .O(aci));
AND2 XLXI_3 (.I0(ci), .I1(b), .O(bci));
OR3 XLXI_5 (.I0(bci), .I1(aci), .I2(ab), .O(co));
XOR3 XLXI_4 (.I0(ci), .I1(b), .I2(a), .O(do));
endmodule

