// C:\XILINX\PROJECTS\ALU16BIT
// Verilog Test fixture created by
// HDL Bencher 5.1i
// Wed Oct 29 19:43:10 2003
// 
// Notes:
// 1) This test fixture has been automatically generated from
//   your Test Bench Waveform
// 2) To use this as a user modifiable test fixture do the following:
//   - Save it as a file with a .tf extension (i.e. File->Save As...)
//   - Add it to your project as a testbench source (i.e. Project->Add Source...)
// 

`timescale 1ns/1ns

module testbench;
	reg CI;
	reg [1:0] Operation;
	reg [15:0] a;
	reg [15:0] b;
	wire CO;
	wire [15:0] Result;
	wire overflow;

	alu16bit UUT (
		.CI(CI),
		.Operation(Operation),
		.a(a),
		.b(b),
		.CO(CO),
		.Result(Result),
		.overflow(overflow)
	);

	integer TX_FILE;
	integer TX_ERROR;

initial
begin
	TX_ERROR=0;
	TX_FILE=$fopen("results.txt");

	// --------------------
	CI = 1'b0;
	Operation = 2'b00; //0
	a = 16'b0000000000000000; //0
	b = 16'b0000000000000000; //0
	// --------------------
	#100 // Time=100 ns
	// --------------------

	if (TX_ERROR == 0) begin
		$display("No errors or warnings");
		$fdisplay(TX_FILE,"No errors or warnings");
	end else begin
		$display("%d errors found in simulation",TX_ERROR);
		$fdisplay(TX_FILE,"%d errors found in simulation",TX_ERROR);
	end

	$fclose(TX_FILE);
	$stop;

end

task CHECK_CO;
	input NEXT_CO;

	#0 begin
		if (NEXT_CO !== CO) begin
			$display("Error at time=%dns CO=%b, expected=%b",
				$time, CO, NEXT_CO);
			$fdisplay(TX_FILE,"Error at time=%dns CO=%b, expected=%b",
				$time, CO, NEXT_CO);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_Result;
	input [15:0] NEXT_Result;

	#0 begin
		if (NEXT_Result !== Result) begin
			$display("Error at time=%dns Result=%b, expected=%b",
				$time, Result, NEXT_Result);
			$fdisplay(TX_FILE,"Error at time=%dns Result=%b, expected=%b",
				$time, Result, NEXT_Result);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_overflow;
	input NEXT_overflow;

	#0 begin
		if (NEXT_overflow !== overflow) begin
			$display("Error at time=%dns overflow=%b, expected=%b",
				$time, overflow, NEXT_overflow);
			$fdisplay(TX_FILE,"Error at time=%dns overflow=%b, expected=%b",
				$time, overflow, NEXT_overflow);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

endmodule
