Hardware Labs

This site contains materials that we are using in our VLSI sequence to produce four  hardware labs using custom integrated circuits to provide a hands-on experience with integrated circuit concepts difficult to simulate. We are providing on this site (i) a summary of each lab and the expected results from the lab,  and (ii) materials that can help instructors use these hardware labs in their courses, including pin lists to create a boards for the integrated circuits, lab proceedures we have used in our courses, and the cif files necessary to fabricate the circuits on a tiny chip on the AMI 0.6um process.

PLEASE CONTACT ME AT THE FOLLOWING EMAIL ADDRESS IF YOU ARE USING THESE MATERIALS SO WE CAN ADD THAT INFORMATION TO OUR NSF GRANT REPORT. I would appreciate it if you would tell me your institution's name and the courses that you will use these labs in.

Digital Lab

The Digital Lab demonstrates the effects of clock skew and power/ground bounce on an array of flip-flops by using two integrated circuits. The clock skew chip contains a parallel layout for the power and ground rails of the flip-flop array and a serpentine layout for the clock. The power-ground bounce chip contains an H-tree distribution for the clock and a serpentine distribution for the rails. In the prelab, the students see the differences in the layout (one chip using proper layout proceedures for the rails and the other using proper layout proceedures for the clock) so that may compare proper and improper layout proceedures. In the experimental part of the lab, the students measure the clock skew and the ground bounce and examine the effects of these nonidealities on the latching of the flip-flops.

Analog and Mixed Signal Labs

Mirrors Lab

The Mirrors Lab demonstrates the effects of process variation and nonidealities on transistors and current mirror circuits. In the prelab, the students observe the layout showning various methods of laying out current mirrors. In the experimental part of the lab, the students observe the effects of (i) process variation on individual transistors on opposite sides of the chip, (ii) mismatch caused by changes in orientation and changes in transistor type, (iii) oxide encroachment on scaled transistors,  and (iv) layout techniques (such as common centroid layout) to prevent process variations on an array of mirrors.

Substrate Noise Lab (still revising)

The Substate Noise Lab demonstrates the effects of digital circuits on nearby analog circuits. This i.c. contains a large inverter chain placed next to a transconductance amplifier. Without any further protection, the inverter chain induces noise onto the transconductance amp via capacitive coupling and substrate noise. The same circuit is placed in a different location of the chip with the addition of guard rings to absorb the substrate noise and an analog shield wire to prevent capacitive coupling. These layout techniqes significantly reduce the effects of the substrate noise on the output voltage of the transconductance amp. Additionally, this lab compares the effects of cross-coupled input FETs and cascoded bias current mirrors on the behavior of the transconductance amplifier.

Please let us know if you have any difficulties or suggested improvements on these labs or materials.

This site is maintained by TinaHudson

NSF Logo

Partial support for the design of these lab materials was provided by the National Science Foundation's Course, Curriculum and Laboratory Improvement Program under grant DUE-0088489.
Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the National Science Foundation.