ECE 333 DIGITAL SYSTEMS

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Instructor:
MIHAELA   ELENA RADU

Required Textbook: Stephen Brown and Zvonko Vranesic, “Fundamentals of Digital Logic with Verilog Design”, McGraw-Hill Companies, Inc., second edition, 2007.

 References (recommended books)

John F. Wakerly “Digital Design Principles and Practices” 4th Edition Updated, Prentice-Hall, 2006.

Michael D. Ciletti “Advanced Digital Design with the Verilog HDL”, Pearson Education, Inc., Upper Saddle River, New Jersey 07458, 2003.

Janick Bergeron, “Writing testbenches-functional Verification of HDL Models”, second edition, Springer, 2003.

 


Prereq: ECE130-Introduction to Logic Design, 

ECE 200-Circuits and Systems,

ECE250-Electronic Device Modeling

Course Grading: 

Homework:                                10%

 Prelabs:                                       5%

Lab notebooks (lab reports):     10%

Exams (3):                           20 % each

Design Project :                            15%

In-class participation:                3% (extra points)

The cumulative score must be at a passing level (i.e>= 60%) in order to pass the course.

All lab works (prelabs, lab  notebooks), design project  and 60% of all Hws must be submitted in order to pass the course.

 

 

 


 

 Course description:

This course is intended to provide you with the experience of building digital systems with time-to-market as a primary component. ECE130 provided you with the  basic building blocks of digital systems. In today's industry, large systems are not implemented using discrete components. They are typically designed by one of two methods: either an integrated circuit is designed (subject of the VLSI courses) or an existing integrated circuit that may be programmed is used (programmable logic device =PLD).

 On the first part of the course  we will focus on designing combinational and sequential digital systems using the Hardware Description Language Verilog by programming PLDs.

Other important concepts related to digital design will be covered also, such as handshaking between FSM, impediments to synchronous design, data path and controller partition design.

   On the second part of the course we will focus on  the analog nature of digital circuits. While ECE130 treated the output of all digital components as  ideal “1” and “0”,  clocks as perfect square waves, this course will address the fact that all digital gates are made out of analog transistors. The analog characteristics of the gates limit the maximum speed of the circuits, affect how many gates can be connected together, cause noise to be induced from one circuit to another, etc. It is in conquering these analog realities that state of the art, high speed, low power  digital designs are created.

 Course objectives:

 By the end of this course,  the students should be able to:

  •  Design the combinational and sequential logic for digital systems from a problem statement,
  • Write Verilog code describing combinational and sequential systems,
  • Write a testbench for combinational and sequential systems using Verilog,
  • Successfully  program GAL and FPGAs chips,
  • Design basic CMOS logic structures using transistors,
  • Calculate the AC and DC characteristics of  CMOS and TTL logic  families,
  • Describes mechanisms by which CMOS gates dissipate power,
  • Design circuits that minimize transmission line effects  that influence signal integrity,
  • Produce a truth table from a PLDs fuse-map and vice versa.

Homework procedures:

 Homework  will be assigned weekly. Late homework will not be accepted  unless arrangements have been made prior to deadline.  If solutions have been posted, assignments will be returned un-graded. Sketches, schematics and plots must be neat and labeled clearly.

Laboratory Procedures:

Labs are performed in groups of two students in  D115.  Lab is a group effort and therefore labs grades will be assigned to the entire group. Each partner must obtain a lab notebook. The lab notebook  is to be a running record of your work in the lab, including the assigned “prelab” activities.

 Missed labwork must be made regardless of the reason the lab was missed.  A late penalty of 10% - grade reduction per day will apply unless previous arrangement for absence have been made. The instructor has the option to reorganize the lab groups.

In class  participation

Please come to class prepared! If you keep up with the course assigned-reading, weekly home-works and laboratory assignments you will be in an excellent position for class participation and for grasping more complex concepts.  From time to time I will expect each student to participate in class by solving  different exercises, contributing within a group, or demonstrating a particular concept through in-class quizzes.

 

 

 

 

 

Last modified: Wednesday August 31, 2011