FPGA Multi-Module System Design

Introduction

In this laboratory, you will develop a multi-module system to implement the PWM-Based DAC from Lab 3. You already have the verilog file for the PWM. In addition, you must create a new verilog file to implement the function of the 555 timer.  This new clock will receive an input from the 8 switches on the I/O board which will set the sampling frequency. The switches must be debounced. Therefore, we will provide you a file that will debounce the inputs. You must connect all of these blocks together using a top-level file.

Objectives

Parts List

Equipment

Software

Prelab

1. Develop a schematic of your sampling frequency clock. This block must use the 50MHz clock to drive it and produce a range of clock frequencies that varies from 50MHz to approximately 1.5kHz. To help you with your design, answer the following questions:
   1. How many bits does my counter need to divide the 50MHz clock down to 1.5kHz?
   2. How do I achieve a 50MHz clock using the frequency divider provided in class?
   3. How can I achieve this frequency range when I only have 8 input switches? (Hint: not all inputs to the counter need to come from the switches. Which ones should be tied to what signal?)
       
2. Create a Verilog description of the sampling frequency clock. Verify your design using a smaller counter and a smaller number of input bits. Include your .v file, your testbench file, and an annotated waveform explaining your simulation results.
    
3. Create a top-level Verilog description that calls the sampling frequency clock, the PWM, and the debouncing circuits (debounce.v and debounceTB.v in case you want to look at my testbench file) and connects them appropriately.  Verify your design (you may want to verify using the smaller counter to save simulation time). Be sure to set up your testbench so that the inputs bounce to verify that the debouncing circuit will correctly eliminate this undesired behavior. Include your .v files, your testbench file, and an annotated waveform explaining your simulation results.
    
4. Review the "Test your design" section of the FPGA Design Flow document to review the proper methods of using the breadboard with the controller board.
    
5. A photocopy of your prelab pages is due at the beginning of the class the day before lab.

Lab

1. Carry out the complete implementation process for your DAC.
    
2. Set up the 74HC4040 counter circuit to generate a four-bit input to your DAC on the Xilinx breadboard. Use the Agilent 33120A function/arbitrary waveform generator to generate the squarewave clock signal needed by your counter circuit.

   DO NOT use the power bus on the Xilinx breadboard for anything! Use the bench power supply to generate the power for all elements on the bread board, but be sure to connect the bench power supply ground to the breadboard ground to prevent ground loops.

   Use the ground bus on the Xilinx breadboard for the ground of your counter and the ground for your function generator.

   Verify that your counter circuit works correctly BEFORE connecting it to the controller board. Specifically, be certain that your inputs do not exceed 5V.

   Connect your input to the controller board through 400-500 ohm resistors to prevent blowing pins on the FPGA.
    

3. Set the switches to obtain the minimum sampling frequency. Verify that the digital output of your PWM is operating correctly.
    
4. Connect the digital output to the low-pass filter built on the breadboard (use the breadboard ground for the filter).  Make sure your series resistor is greater than 500 ohms.
    
5. Demonstrate your DAC circuit to the instructor.
    
6. Change the switches and observe the effect increasing the sampling frequency has on the DAC output.
    

All done!