/* Solution to the lock Meely machine described in homework 1.*/

module lock(clock, reset, A, B, L);

input clock, reset, A, B;
output L;		

reg L; 
reg [2:0] state, nextstate;	//state variables for the state machine
 
parameter s0=3'b000, xB=3'b001, xBB=3'b010, xBBA=3'b011, inactive=3'b100;

//state register 
always @ (posedge clock or posedge reset)
   if (reset)      
	state <= s0;
   else         
	state <= nextstate;

//next state decoder
always @ (state or A or B)
	case (state)
	s0:	if (B)
			nextstate<=xB;
			else
			nextstate<=(A)? inactive:s0;
	xB:	if (B)
			nextstate<=xBB;
		else  nextstate<=(A)? inactive:xB;
	xBB:	if (A)
			nextstate<=xBBA;
		else	nextstate<=(B)? inactive:xBB;
	xBBA:	nextstate<= (A|B)? inactive:xBBA;
	inactive: nextstate<= inactive;
	//default: nextstate<=s0;
	endcase

//output decoder
always @ (state or A or B or reset)
	case (state)
	reset: L<=0;
	xB:	L<=0;
	xBB:	L<=0;
	xBBA: L<= reset;
	inactive: L<=0;
	endcase

endmodule