module CounterUD(i$clock, i$Reset, i$Enable, i$Sel, o$Q);

//Port modes  
input i$clock, i$Reset, i$Enable, i$Sel; 
output [3:0] o$Q;

//Registered identifiers
reg [3:0] o$Q;

//Functionality

always @ (posedge i$clock or posedge i$Reset)
	if (i$Reset == 0)
		o$Q<=0;
	else if (i$Sel == 1)
		o$Q<= (i$Enable) ? o$Q : o$Q+3;
	else
		o$Q<= (i$Enable) ? o$Q : o$Q-5;

endmodule