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Zachary J. Estrada

Assistant Professor of Electrical and Computer Engineering

Dr. Estrada’s expertise in systems engineering has been useful as a scholar and an engineer with the Chicago Mercantile Exchange Group. He teaches classes that introduce students to digital and embedded systems. Dr. Estrada is a member of the technical program committee for the International Conference on Computing, Networking and Communications, and a member of the Linux Foundation.

Teaching Interests

  • Computer systems
  • Computer security and reliability
  • Fault tolerance
  • Virtualization

Research Experiences

  • Cloud computing
  • High availability systems

Select Publications & Presentations

  • Wang, G., Estrada, Z.J., Pham, C., Kalbarczyk, Z. and Iyer, R. K., “Hypervisor Introspection: A Technique for Evading Passive Virtual Machine Monitoring,” USENIX Workshop on Offensive Technologies (WOOT 15), USENIX Association, Washington, D.C., 2015
  • Estrada, Z. J., Pham, C., Deng, F., Yan, L., Kalbarczyk, Z. and Iyer, R. K., “Dynamic VM Dependability Monitoring Using Hypervisor Probes,” Dependable Computing Conference, European Institute of Electrical and Electronic Engineers, 61-72, 2015
  • Estrada, Z. J., Deng, F., Stephens, Z., Pham, C., Kalbarczyk, Z. and Iyer, R. K., “Performance Comparison and Tuning of Virtual Machines for Sequence Alignment Software,” Scalable Computing: Practice and Experience, Vol. 16 (1), 2015
  • Estrada, Z. J., Stephens, Z., Pham, C., Kalbarczyk, Z. and Iyer, R. K., “A Performance Evaluation of Sequence Alignment Software in Virtualized Environments,” International Workshop on Cloud for Bio (C4Bio), IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing, Institute of Electrical and Electronic Engineers, 730-737, 2014
  • Pham, C., Estrada, Z., Cao, P., Kalbarczyk, Z. and Iyer, R. K., “Reliability and Security Monitoring of Virtual Machines Using Hardware Architectural Invariants,” International Conference on Dependable Systems and Networks, Institute of Electrical and Electronic Engineers/International Federation for Information Processing, 13-24, 2014
  • Pham, C., Li, Q., Estrada, Z., Kalbarczyk, Z. and Iyer, R. K., “A Simulation Framework to Evaluate Virtual CPU Scheduling Algorithms,” Distributed Computing Systems Workshops, IEEE International Conference on Distributed Computing Systems, Institute of Electrical and Electronic Engineers, 138-143, 2013
  • Estrada, Z. J., Dellabetta, B., Ravaioli, U. and Gilbert, M., “Phonon-Limited Transport in Graphene Pseudospintronic Devices,” Electron Device Letters, Institute of Electrical and Electronic Engineers, Vol. 33 (10), 1,465-1,467,  2012

Academic Degrees

  • PhD, University of Illinois at Urbana-Champaign, 2016
  • MS, University of Illinois at Urbana-Champaign, 2012
  • BS, Illinois Institute of Technology, 2009