CALL FOR PARTICIPATION

WORKSHOP ON BINARY TRANSLATION

In Conjunction with the International Conference on Parallel Architectures and Compilation Techniques (PACT '99) http://www.rose-hulman.edu/PACT/

Newport Beach, California, USA October 16, 1999

OBJECTIVE

Although long employed by industry, large scale use of binary translation and on-the-fly code generation has only recently become common, and results have been published in widely scattered publications.

The main objective of this workshop is to bring together researchers and practitioners with the aim of stimulating the exchange of ideas and experiences on the potential and limits of binary translation, and opening new avenues of research.

KEYNOTE ADDRESS

Dick Sites, architect of the DEC/Compaq Alpha and leader of the FX!32, VEST, and mx binary translation projects will present a 1 hour keynote address on "Historical Perspectives on Binary Translation".

WORKSHOP REGISTRATION

Registration for the PACT'99 conference permits attendance at the workshop at no extra charge. However, please indicate on the registration form that you are interested in attending the Binary Translation Workshop. NOTE: You must register for PACT'99 in order to attend the workshop.

ORGANIZERS

Workshop Co-Chairs: Yaron Sheffer (Intel) and Erik Altman (IBM)

yaron.sheffer@intel.com or erik@watson.ibm.com

Program Committee:

 
Brad Calder          >   University of California - San Diego
Evelyn Duesterwald   >   HP Labs
Kemal Ebcioglu       >   IBM T.J. Watson Research
Michael Franz        >   University of California - Irvine
Michael K. Gschwind  >   IBM T.J. Watson Research
Ray Hookway          >   Compaq
David Kaeli          >   Northeastern University
David Keppel         >   Transmeta
Andreas Krall        >   Technical University of Vienna
James R. Larus       >   Microsoft Research
David J. Lilja       >   University of Minnesota
Soo-Mook Moon        >   Seoul National University
Sumedh Sathaye       >   IBM T.J. Watson Research
Michael Smith        >   Harvard University

DETAILS

This workshop is intended to be a forum for bringing together researchers in the area of binary translation. Talks will be presented emphasizing new ideas and experience with building binary translation systems. There will be a limited number of talks in order to allow the audience to participate.

TOPICS OF INTEREST INCLUDE, BUT ARE NOT LIMITED TO:

• Dynamic (Runtime) Translation
  • With operating system support
  • Without operating system support
  • Java
  • From traditional architectures such as Alpha, IA32, MIPS, PowerPC, and SPARC to new architectures
• Static Translation
  • With no runtime assistance/translation
  • With runtime assistance/translation (Hybrid Translation)
• General techniques and problems
  • Compatibility
    • Self-modifying code
    • Self-referential code
    • Precise exceptions
    • Other issues
  • Scheduling and optimization
  • Adapting code to changing program behavior
  • On-the-fly reconstruction of CFG's and data dependences
  • Management of translated code
  • Other compilation challenges
• Hardware Support
  • Hardware Assists for Binary Translation
    • Interpretation Engines
    • Profiling Branch Directions, Instructions with Cache Misses, etc.
    • Other Assists
  • Hardware Mechanisms Employing Binary Translation Techniques
    • Pipeline cracking CISC operations into micro-ops, a la Pentium Pro
    • Cached hardware schedules a la DIF
    • Other Mechanisms

Workshop attendees will receive copies of all papers presented.