Resources

MIPS

MIPS pdf

Xilinx

Xess

 WHAT'S NEW?

9-7-01 

• Decided on MIPS32 Instruction Set Architecture(with many instruction eliminated from implementation)

9-18-01 

• Added Instruction Set Architecture format

10-1-01

•  Added format of how Memory was going to be broken up

10-28-01

•  Added opcodes and RTL

CPU

Opcodes

RTL

Peripherals

Resources and Status Reports

Compiler

Operating System

Resources/Links

Contact Information

CPU TEAM

• michael.c.simon@rose-hulman.edu
• jonathan.b.labayo@rose-hulman.edu
• garrick.l.dasbach@rose-hulman.edu

Peripherals:

• david.j.perenic@rose-hulman.edu
• david.j.wicke@rose-hulman.edu
• jennifer.c.lay@rose-hulman.edu

Compiler:

• john.f.glattfelt@rose-hulman.edu
• sarah.b.greenlee@rose-hulman.edu
• peter.c.bryson@rose-hulman.edu
• alan.r.balasundaram@rose-hulman.edu

Operating System:

• alla.genkina@rose-hulman.edu
• jarrod.k.gray@rose-hulman.edu
• sandor.a.pethes@rose-hulman.edu