module slowclock_TB;
reg clock, reset;
wire slowclock;

slowclock  DUT(.clock(clock),
            .reset(reset),
            .slowclock(slowclock)
           );
            
initial
begin


reset=1;
clock=0;
#2
reset=0;
#20
$finish;
end
always #1 clock=~clock;
endmodule