This laboratory will give you confidence to use the CAD tools associated with targeting a Verilog description to a Xilinx Spartan FPGA board.

In this lab, you will be using the main controller board. You will design a character message that can be displayed on the 4-digit 7-segment display. The message must be  4 characters long (different characters). You can use numbers, letters, or any character of your design. Be creative. Be certain to read the users manual of the  board before designing your circuit so  you know how to properly drive the 7-segment display. Also, look at the functionality of the push buttons so  you will know whether the reset for your system should be active high or active low. (The slide switches cannot be used currently because they must be de-bounced. We will discuss how to de-bounce switches in one of the next lectures.)

A few notes about the  Four-Digit,  Seven -Segment  LED display of your Xilinx  Spartan-3 FPGA board :

1) All 12 signals ( four Enable signals, one for each digit, the cathodes of each of the 7 segments, and the cathode of the decimal point) of the 7-segment display must be activated at something at all times. The LED  enable signals are time-multiplexed to display data on all four characters.   Through persistence of vision, the human brain perceives that all four character appear simultaneously, similar to the way the brain perceives a TV display.  This "scanning techniques" reduces the number of I/O pins required for the four characters and  reduce power dissipation.

2. The entire system must be driven by the 50MHz master clock. You can divide this clock down to the frequency necessary by the refresh rate, which may take  values  between 60 Hz and 1 kHz.  At these refresh rates, the human brain perceives that all four character appear simultaneously.

The Verilog code given to you in the sequential notes may be used to do the clock division. If your system is driven by the clock edge, you do not need a 50% duty cycle for your system to operate correctly. See clock divider on the PP presentation. To understand how it works   use the the following Verilog files slowclock.v and slowclock_TB.v for simulation.

3) The display must be tied to the master reset. 

No additional parts required for this lab.  Everything is contained in the development kit.

1. Review the users manual of the board. All of the Xilinx FPGA  board descriptions can be found at the following web site
2.  http://www.digilentinc.com/ .
3. Design the truth table necessary to drive each of the 7 segments for your character set. Please show  what the character set is supposed to look like  when displayed  on the Seven-Segment-LED display. See the user manual for Nexys board to see if the  enable signals, the cathodes of each of the 7 segments, and the cathode of the decimal point are  active high or low? (The enable signals are called  AN[3:0]-anode control signals).
    
4. Select  the refresh rate necessary for your design.
    
5. Calculate the size of the counter necessary to obtain your refresh rate from the 50MHz clock. (See clock divider on the  "Sequential Circuits in Verilog" Power Point presentation)
    
6. Write the Verilog code for your design (Note: you may want to use a parameterized statement for the maxcount and make it much smaller for the simulation). Otherwise, the simulation will take a HUGE amount of time. Be sure to change it back before you come into lab. Turn in your display.v file.
    
7. Write  a test bench to verify your design. Turn in your test bench file and provide an annotated timing diagram  showing your results.  (Comment your results).  A photocopy of your prelab pages is due at the beginning of the class the day before lab.
8. Study carefully the  Design Flow document, valid for Xilinx Webpack ISE  9.2, working under Windows. 
9. See http://ece-1.rose-hulman.edu/cadhelp/   to find more information about the software tools used in this lab  and the design and implementation steps.

1. Carry out the complete implementation process for your character generator.
    
2. Demonstrate your character generator circuit to the instructor.